16.1.10 Velocity x Counter Hold Register

Name:	VELxHLD
Offset:	0x15A, 0x183, 0x55A


Bit	15	14	13	12	11	10	9	8
	VELHLD[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	VELHLD[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – VELHLD[31:16] Hold for Reading/Writing Velocity x Counter High Word Register VELxCNTH (VELxCNT[31:16]) bits

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