17.5.2 UARTx Configuration Register High
| Name: | UxMODEH |
| Offset: | 0x23A, 0x262, 0xF02 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SLPEN | ACTIVE | BCLKMOD | BCLKSEL[1:0] | HALFDPLX | |||||
| Access | R/W | R | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNOVF | URXINV | STSEL[1:0] | C0EN | UTXINV | FLO[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – SLPEN Run During Sleep Enable bit
| Value | Description |
|---|---|
1 |
UART BRG clock runs during Sleep |
0 |
UART BRG clock is turned off during Sleep |
Bit 14 – ACTIVE UART Running Status bit
| Value | Description |
|---|---|
1 |
UART clock request is active (user can not update the UxMODE/UxMODEH registers) |
0 |
UART clock request is not active (user can update the UxMODE/UxMODEH registers) |
Bit 11 – BCLKMOD Baud Clock Generation Mode Select bit
| Value | Description |
|---|---|
1 |
Uses fractional Baud Rate Generation |
0 |
Uses legacy divide-by-x counter for baud clock generation (x = 4 or 16 depending on the BRGH bit) |
Bits 10:9 – BCLKSEL[1:0] Baud Clock Source Selection bits
| Value | Description |
|---|---|
11 |
AFVCO/3 |
10 |
FOSC |
01 |
Reserved |
00 |
FOSC/2 (FP) |
Bit 8 – HALFDPLX UART Half-Duplex Selection Mode bit
| Value | Description |
|---|---|
1 |
Half-Duplex mode: UxTX is driven as an output when transmitting and tri-stated when TX is Idle |
0 |
Full-Duplex mode: UxTX is driven as an output at all times when both UARTEN and UTXEN are set |
Bit 7 – RUNOVF Run During Overflow Condition Mode bit
| Value | Description |
|---|---|
1 |
When an Overflow Error (OERR) condition is detected, the RX shifter continues to run so as to remain synchronized with incoming RX data; data are not transferred to UxRXREG when it is full (i.e., no UxRXREG data are overwritten) |
0 |
When an Overflow Error (OERR) condition is detected, the RX shifter stops accepting new data (Legacy mode) |
Bit 6 – URXINV UART Receive Polarity bit
| Value | Description |
|---|---|
1 |
Inverts RX polarity; Idle state is low |
0 |
Input is not inverted; Idle state is high |
Bits 5:4 – STSEL[1:0] Number of Stop Bits Selection bits
| Value | Description |
|---|---|
11 |
2 Stop bits sent, 1 checked at receive |
10 |
2 Stop bits sent, 2 checked at receive |
01 |
1.5 Stop bits sent, 1.5 checked at receive |
00 |
1 Stop bit sent, 1 checked at receive |
Bit 3 – C0EN Enable Legacy Checksum (C0) Transmit and Receive bit
| Value | Description |
|---|---|
1 |
Checksum Mode 1 (enhanced LIN checksum in LIN mode; add all TX/RX words in all other modes) |
0 |
Checksum Mode 0 (legacy LIN checksum in LIN mode; not used in all other modes) |
Bit 2 – UTXINV UART Transmit Polarity bit
| Value | Description |
|---|---|
1 |
Inverts TX polarity; TX is low in Idle state |
0 |
Output data are not inverted; TX output is high in Idle state |
Bits 1:0 – FLO[1:0] Flow Control Enable
bits (only valid when MOD[3:0] =
0xxx)
| Value | Description |
|---|---|
11 |
Reserved |
10 |
RTS-DSR (for TX side)/CTS-DTR (for RX side) hardware flow control |
01 |
XON/XOFF software flow control |
00 |
Flow control off |