17.5.3 UARTx Status Register
Legend: HC = Hardware Clearable bit; HS = Hardware Settable bit
| Name: | UxSTA |
| Offset: | 0x23C, 0x264, 0xF04 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXMTIE | PERIE | ABDOVE | CERIE | FERIE | RXBKIE | OERIE | TXCIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRMT | PERR | ABDOVF | CERIF | FERR | RXBKIF | OERR | TXCIF | ||
| Access | R | R | R/W/HS | R/W/HC | R | R/W/HC | R/W/HC | R/W/HC | |
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – TXMTIE Transmit Shifter Empty Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 14 – PERIE Parity Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 13 – ABDOVE Auto-Baud Rate Acquisition Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 12 – CERIE Checksum Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 11 – FERIE Framing Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 10 – RXBKIE Receive Break Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 9 – OERIE Receive Buffer Overflow Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 8 – TXCIE Transmit Collision Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled |
0 |
Interrupt is disabled |
Bit 7 – TRMT Transmit Shifter Empty Interrupt Flag bit (read-only)
| Value | Description |
|---|---|
1 |
Transmit Shift Register (TSR) is empty (end of last Stop bit when STPMD =
|
0 |
Transmit Shift Register is not empty |
Bit 6 – PERR Parity Error/Address Received/Forward Frame Interrupt Flag bit
LIN and Parity Modes:
1 = Parity error detected
0 = No parity error detected
Address Mode:
1 = Address received
0 = No address detected
All Other Modes:
Not used.
Bit 5 – ABDOVF Auto-Baud Rate Acquisition Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
BRG rolled over during the auto-baud rate acquisition sequence (must be cleared in software) |
0 |
BRG has not rolled over during the auto-baud rate acquisition sequence |
Bit 4 – CERIF Checksum Error Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
Checksum error |
0 |
No checksum error |
Bit 3 – FERR Framing Error Interrupt Flag bit
| Value | Description |
|---|---|
1 |
Framing Error: Inverted level of the Stop bit corresponding to the topmost character in the buffer; propagates through the buffer with the received character |
0 |
No framing error |
Bit 2 – RXBKIF Receive Break Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
A Break was received |
0 |
No Break was detected |
Bit 1 – OERR Receive Buffer Overflow Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
Receive buffer has overflowed |
0 |
Receive buffer has not overflowed |
Bit 0 – TXCIF Transmit Collision Interrupt Flag bit (must be cleared by software)
| Value | Description |
|---|---|
1 |
Transmitted word is not equal to the received word |
0 |
Transmitted word is equal to the received word |