17.5.1 UARTx Configuration Register
- R/HS/HC in DMX and LIN mode.
Legend: HC = Hardware Clearable bit; HS = Hardware Settable bit
| Name: | UxMODE |
| Offset: | 0x238, 0x260, 0xF00 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UARTEN | USIDL | WAKE | RXBIMD | BRKOVR | UTXBRK | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W/HC | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BRGH | ABAUD | UTXEN | URXEN | MOD[3:0] | |||||
| Access | R/W | R/W/HC | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – UARTEN UART Enable bit
| Value | Description |
|---|---|
1 |
UART is ready to transmit and receive |
0 |
UART state machine, FIFO Buffer Pointers and counters are reset; registers are readable and writable |
Bit 13 – USIDL UART Stop in Idle Mode bit
| Value | Description |
|---|---|
1 |
Discontinues module operation when device enters Idle mode |
0 |
Continues module operation in Idle mode |
Bit 12 – WAKE Wake-up Enable bit
| Value | Description |
|---|---|
1 |
Module will continue to sample the RX pin – interrupt generated on falling edge, bit cleared in hardware on following rising edge; if ABAUD is set, Auto-Baud Detection (ABD) will begin immediately |
0 |
RX pin is not monitored nor rising edge detected |
Bit 11 – RXBIMD Receive Break Interrupt Mode bit
| Value | Description |
|---|---|
1 |
RXBKIF flag when a minimum of 23 (DMX)/11 (asynchronous or LIN/J2602) low bit periods are detected |
0 |
RXBKIF flag when the Break makes a low-to-high transition after being low for at least 23/11-bit periods |
Bit 9 – BRKOVR Send Break Software Override bit
Overrides the TX Data Line:
| Value | Description |
|---|---|
1 |
Makes the TX line active (Output 0 when UTXINV = |
0 |
TX line is driven by the shifter |
Bit 8 – UTXBRK UART Transmit Break bit(1)
| Value | Description |
|---|---|
1 |
Sends Sync Break on next transmission; cleared by hardware upon completion |
0 |
Sync Break transmission is disabled or has completed |
Bit 7 – BRGH High Baud Rate Select bit
| Value | Description |
|---|---|
1 |
High Speed: Baud rate is baudclk/4 |
0 |
Low Speed: Baud rate is baudclk/16 |
Bit 6 – ABAUD Auto-Baud Detect
Enable bit (read-only when MOD[3:0] =
1xxx)
| Value | Description |
|---|---|
1 |
Enables baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion |
0 |
Baud rate measurement is disabled or has completed |
Bit 5 – UTXEN UART Transmit Enable bit
| Value | Description |
|---|---|
1 |
Transmit enabled – except during Auto-Baud Detection |
0 |
Transmit disabled – all transmit counters, pointers and state machines are reset; TX buffer is not flushed, status bits are not reset |
Bit 4 – URXEN UART Receive Enable bit
| Value | Description |
|---|---|
1 |
Receive enabled – except during Auto-Baud Detection |
0 |
Receive disabled – all receive counters, pointers and state machines are reset; RX buffer is not flushed, status bits are not reset |
Bits 3:0 – MOD[3:0] UART Mode bits
| Value | Description |
|---|---|
| Other |
Reserved |
1111 |
Smart card |
1110 |
IrDA® |
1101 |
Reserved |
1100 |
LIN Commander/Responder |
1011 |
LIN Responder only |
1010 |
DMX |
1001 |
Reserved |
1000 |
Reserved |
0111 |
Reserved |
0110 |
Reserved |
0101 |
Reserved |
0100 |
Asynchronous 9-bit UART with address detect, ninth bit = |
0011 |
Asynchronous 8-bit UART without address detect, ninth bit is used as an even parity bit |
0010 |
Asynchronous 8-bit UART without address detect, ninth bit is used as an odd parity bit |
0001 |
Asynchronous 7-bit UART |
0000 |
Asynchronous 8-bit UART |