15.4.6 DACx Data Low Register
| Name: | DACxDATL |
| Offset: | 0xC54, 0xC64, 0xC74, 0xC84, 0xC94, 0xCA4 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DACLOW[11:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DACLOW[11:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 11:0 – DACLOW[11:0] DACx Low Data bits
In Hysteretic mode, Slope Generator mode and Triangle mode, this register specifies the low data value and/or limit for the DACx module. Valid values are from 205 to 3890.