15.4.5 DACx Control High Register
| Name: | DACxCONH |
| Offset: | 0xC52, 0xC62, 0xC72, 0xC82, 0xC92, 0xCA2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TMCB[9:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMCB[9:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 9:0 – TMCB[9:0] DACx Leading-Edge Blanking bits
These register bits specify the blanking period for the comparator, following changes to the DAC output during Change-of-State (COS), for the input signal selected by the HCFSEL[3:0] bits in SLPxCONL.