15.4.1 DAC Control 1 Low Register

Note:

These bits should only be changed when DACON = 0 to avoid unpredictable behavior.

Name:	DACCTRL1L
Offset:	0xC48


Bit	15	14	13	12	11	10	9	8
	DACON		DACSIDL
Access	R/W		R/W
Reset	0		0


Bit	7	6	5	4	3	2	1	0
	CLKSEL[1:0]		CLKDIV[1:0]			FCLKDIV[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0

Bit 15 – DACON Common DAC Module Enable bit

Value	Description
1	Enables DAC modules
0	Disables DAC modules and disables FSCM clocks to reduce power consumption; any pending Slope mode and/or Underflow conditions are cleared

Bit 13 – DACSIDL DAC Stop in Idle Mode bit

Value	Description
1	Discontinues module operation when device enters Idle mode
0	Continues module operation in Idle mode

Bits 7:6 – CLKSEL[1:0] DAC Clock Source Select bits⁽¹⁾

Value	Description
11	F_PLLO
10	AF_PLLO
01	F_VCO/2
00	AF_VCO/2

Bits 5:4 – CLKDIV[1:0] DAC Clock Divider bits⁽¹⁾

Value	Description
11	Divide-by-4
10	Divide-by-3 (non-uniform duty cycle)
01	Divide-by-2
00	1x

Bits 2:0 – FCLKDIV[2:0] Comparator Filter Clock Divider bits

Value	Description
111	Divide-by-8
110	Divide-by-7
101	Divide-by-6
100	Divide-by-5
011	Divide-by-4
010	Divide-by-3
001	Divide-by-2
000	1x

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