30.2.5 FOSC Configuration Register

Note:

A time-out period will occur when the system clock switching logic requests the PLL clock source and the PLL is not already enabled.

Legend: PO = Program Once bit,

Name:	FOSC
Offset:	0xF1C


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				XTBST	XTCFG[1:0]			PLLKEN
Access				R/PO	R/PO	R/PO		R/PO
Reset				1	1	1		1


Bit	7	6	5	4	3	2	1	0
	FCKSM[1:0]					OSCIOFNC	POSCMD[1:0]
Access	R/PO	R/PO				R/PO	R/PO	R/PO
Reset	1	1				1	1	1

Bit 12 – XTBST Oscillator Kick-Start Programmability bit

Value	Description
`1`	Boosts the kick-start
`0`	Default kick-start

Bits 11:10 – XTCFG[1:0] Crystal Oscillator Drive Select bits

Current gain programmability for oscillator (output drive).

Value	Description
`11`	Gain3 (use for 24-32 MHz crystals)
`10`	Gain2 (use for 16-24 MHz crystals)
`01`	Gain1 (use for 8-16 MHz crystals)
`00`	Gain0 (use for 4-8 MHz crystals)

Bit 8 – PLLKEN PLL Lock Status Control bit⁽¹⁾

Value	Description
1	PLL lock signal will be used to disable PLL clock output if lock is lost
0	PLL lock signal is not used; the PLL clock output will not be disabled if lock is lost

Bits 7:6 – FCKSM[1:0] Clock Switching Mode bits

Value	Description
`1x`	Clock switching is disabled, Fail-Safe Clock Monitor is disabled
`01`	Clock switching is enabled, Fail-Safe Clock Monitor is disabled
`00`	Clock switching is enabled, Fail-Safe Clock Monitor is enabled

Bit 2 – OSCIOFNC OSCO Pin Function bit (except in XT and HS modes)⁽¹⁾

Value	Description
`1`	OSCO is the clock output
`0`	OSCO is the general purpose digital I/O pin

Bits 1:0 – POSCMD[1:0] Primary Oscillator Mode Select bits

Value	Description
`11`	Primary Oscillator is disabled
`10`	HS Crystal Oscillator mode (10 MHz-32 MHz)
`01`	XT Crystal Oscillator mode (3.5 MHz-10 MHz)
`00`	EC (External Clock) mode