3.5.3.8.2 TMCR2 – TX Modulator Control Register 2
| Name: | TMCR2 |
| Offset: | 0x12D |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMMSB | TMSSE | TMPOL | TMNRZE | TMCRCL[1:0] | TMCRCE | ||||
| Access | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
0’ when read.Bit 6 – TMMSB TX Modulator Most Significant Bit First
| TMMSB | Description |
|---|---|
0 |
Data from the DFIFO are sent out (byte-wise) LSB-first. Incomplete bytes must be right/LSB-aligned in the data FIFO. |
1 |
Data from the DFIFO are sent out (byte-wise) MSB-first. Incomplete bytes must be left/MSB-aligned in the data FIFO. |
Bit 5 – TMSSE TX Modulator Stop Sequence Enable
| TMSSE | Description |
|---|---|
0 | Stop sequence generation is disabled. |
1 | A stop sequence is generated according to the configuration of the TMSSC register. The stop sequence is automatically attached to the end of the telegram. |
Bit 4 – TMPOL TX Modulator Polarity
| TMPOL | Description |
|---|---|
0 | Default polarity. Data from the SFIFO, NRZ data and stop
sequence are sent as is. Manchester coding: Rising edge in
the middle of a bit is a ‘1’. |
1 |
Inverse polarity. Data from the SFIFO, NRZ data and stop
sequence are inverted before they are sent:
‘ Manchester coding: Falling edge in the middle of a bit is
a ‘ |
Bit 3 – TMNRZE TX Modulator NRZ Mode Enable
| TMNRZE | Description |
|---|---|
0 | Data from the DFIFO and the CRC checksum are sent out Manchester-coded. The polarity can be configured in TMCR2.TMPOL. The serial output clock has to be configured according to the symbol rate of the signal. This bit has no effect on data from the SFIFO and the stop sequence. |
1 | Data from the DFIFO are not modified and sent out as an NRZ signal. The serial output clock has to be configured according to the signal bit rate. |
Bits 2:1 – TMCRCL[1:0] TX Modulator CRC Length
| TMCRCL1 | TMCRCL0 | Description |
|---|---|---|
0 | 0 | CRC 4-bit |
0 | 1 | CRC 8-bit |
1 | 1 | CRC 16-bit |
1 | 0 | Not used (default 4-bit) |
Bit 0 – TMCRCE TX Modulator CRC Enable
| TMCRCE | Description |
|---|---|
0 | TX CRC calculation is disabled. |
1 | TX CRC calculation is enabled. A CRC checksum is calculated according to the settings in the TMCR2.TMCRCL, TMCPx, TMCIx and TMCSB registers. The checksum is automatically attached to the end of the DFIFO payload. |