3.5.3.8.3 TMSR – TX
Modulator Status Register
| Name: | TMSR |
| Offset: | 0x12C |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | TMTCF | |
| Access | R | R | R | R | R | R | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit always
returns ‘0’ when read.
Bit 7 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 6 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 5 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 4 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 3 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 2 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 1 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 0 – TMTCF TX Modulator
Transmission Complete Status Flag
This flag bit is set after the
number of bits configured in the TMTLx register are sent or after all data from the
FIFOs including the CRC and stop sequence are sent and the FIFOs are empty. The
TMTCF flag can generate an interrupt when masked in TMCR1.TMCIM. The TMTCF flag is
automatically cleared when the interrupt is executed or by writing a
‘1’ to its bit location.
