3.5.3.8.1 TMCR1 – TX Modulator Control Register 1


Bit	7	6	5	4	3	2	1	0
				TMCIM	TMSCS	TMPIS[2:0]
Access	R	R	R	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – Reserved Bit

This bit always returns ‘0’ when read.

Bit 6 – Reserved Bit

This bit always returns ‘0’ when read.

Bit 5 – Reserved Bit

This bit always returns ‘0’ when read.

Bit 4 – TMCIM TX Modulator Transmission Complete Interrupt Mask

Writing this bit to ‘1’ enables the transmission complete interrupt. An interrupt is triggered after SFIFO, DFIFO, CRC and stop sequence processing are complete.


TMCIM	Description
`0`	Transmission complete interrupt is disabled.
`1`	Transmission complete interrupt is enabled.

Bit 3 – TMSCS TX Modulator Serial Output Clock Select

The TMSCS bit selects the serial output clock source of the TX modulator. The clock must be configured to correspond to the symbol rate in Manchester mode and the bit rate in NRZ mode.


TMSCS	Description
`0`	Output clock of Timer2 is used.
`1`	Output clock of Timer3 is used.

Bits 2:0 – TMPIS[2:0] TX Modulator Port Interface Select

These bits select the output signal of the TX modulator port interface to pin 17 (PC3). The corresponding data direction register of the port has to be set to output to enable the driver.


TMPIS2	TMPIS1	TMPIS0	OutputSignalofPin 17/PC3
`0`	`0`	`0`	Port C3 data register
`0`	`0`	`1`	M2 – Output toggle register of Timer2
`0`	`1`	`0`	M3 – Output toggle register of Timer3
`0`	`1`	`1`	M4 – Output toggle register of Timer4
`1`	`0`	`0`	SO4TX – TX modulator shift register serial output
`1`	`0`	`1`	Reserved (Implementation: SO4TX)
`1`	`1`	`0`	Reserved (Implementation: SO4TX)
`1`	`1`	`1`	Reserved (Implementation: SO4TX)

Name:	TMCR1
Offset:	0x12E
Reset:	0x00