2.12.12.1 Service-Specific Configuration

This configuration contains the service-specific part of a service configuration.

Note: The used addresses are for service 0. The addresses for service 1 and service 2 can be found in EEPROM Map.

CHCR

The CHCR variable is a copy of the channel filter configuration register (CHCR) and contains the channel filter configuration settings. See Channel Filter for a functional description, and RX Digital Signal Processing (RX DSP) for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00BB	CHCR	—	—	—	—	BWM[3:0]

Bits 7..4: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 3..0: BWM – Bandwidth Mode

CHDN

The CHDN variable is a copy of the channel filter down-sampling register (CHDN) and contains the channel filter down-sampling settings. See Channel Filter for a functional description, and RX Digital Signal Processing (RX DSP) for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00BC	CHDN	—	—	ADCDN	BBDN[4:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: ADCDN – ADC Down Sampling Configuration

Bits 4..0: BBDN[4:0] – Baseband Filter Down Sampling Ratio

CHSTARTFILTER

The CHSTARTFILTER variable is a copy of the SSM filter bandwidth register (SSMFBR) and contains the channel filter start-up time settings. See Channel Filter for a functional description, and Sequencer State Machine for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00BD	CHSTARTFILTER	—	—	PLDT	HADT	DFDT	FID[2:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: PLDT – PLL Lock Delay Time

Bit 4: HADT – Half Antenna Damping Delay Time

Bit 3: DFDT – Double Filter Delay Time

Bits 2..0: FID – Filter Delay

DMCDA, DMCDB

The DMCDA/B variables are a copy of the demodulator carrier detect registers (DMCDA/B) and contain the demodulator carrier detect settings for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Demodulator and Signal Checks for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00BE	DMCDA	DMCTA[2:0]			DMCLA[4:0]
0x00BF	DMCDB	DMCTB[2:0]			DMCLB[4:0]

Bits 7..5: DMCTA/B[2:0] – Demodulator Carrier Detect Time for Path A/B

Bits 4..0: DMCLA/B[4:0] – Demodulator Carrier Detect Limit for Path A/B

DMCRA, DMCRB

The DMCRA/B variables are a copy of the demodulator control registers (DMCRA/B) and contain the demodulator control settings for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Demodulator and Signal Checks for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00C0	DMCRA	DMARA	SY1TA	SASKA	DMPGA[4:0]
0x00C1	DMCRB	DMARB	SY1TB	SASKB	DMPGB[4:0]

Bit 7: DMARA/B – Demodulator Automatic Restart on Path A/B

Bit 6: SY1TA/B – Symbol Check with 1T only on Path A/B

Bit 5: SASKA/B – Select ASK Input for Path A/B

Bits 4..0: DMPGA/B[4:0] – Demodulator PLL Loop Gain for Path A/B

DMDRA, DMDRB

The DMDRA/B variables are a copy of the demodulator data rate registers (DMDRA/B) and contain the demodulator data rate settings for path A and path B. See Demodulation Settings for a functional description, and Demodulator and Signal Checks for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00C2	DMDRA	DMDNA[3:0]				DMAA[3:0]
0x00C3	DMDRB	DMDNB[3:0]				DMAB[3:0]

Bits 7..4: DMDNA/B – Demodulator Down Sampling on Path A/B

Bits 3..0: DMAA/B – Demodulator Moving Average Data Rate Factor on Path A/B

DMMA, DMMB

The DMMA/B variables are a copy of the demodulator mode registers (DMMA/B) and contain the demodulator operating mode settings for path A and path B. See Demodulation Settings for a functional description, and Demodulator and Signal Checks for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00C4	DMMA	DMNEA	DMHA	DMPA	DMATA[4:0]
0x00C5	DMMB	DMNEB	DMHB	DMPB	DMATB[4:0]

Bit 7: DMNEA/B – Demodulator NRZ Enable for Path A/B

Bit 6: DMHA/B – Demodulator Hold Mode for Path A/B

Bit 5: DMPA/B – Demodulator Received Data Polarity for Path A/B

Bits 4..0:DMATA/B[4:0] – Demodulator Amplitude Threshold for Path A/B

EOT1A, EOT1B

The EOT1A/B variables are a copy of the end of telegram conditions 1 registers (EOTC1A/B) and contain the EOT configuration during WUP check for path A and path B. See RX Telegram Handling for a functional description, and RX DSP Control for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00C6	EOT1A	EOTBFE	RRFEA	TELREA	TMOFEA	MANFEA	SYTFEA	AMPFEA	CARFEA
0x00C7	EOT1B	EOTAFE	RRFEB	TELREB	TMOFEB	MANFEB	SYTFEB	AMPFEB	CARFEB

Bit 7: EOTB/AFE – End of Telegram on Path B/A Fail Enable

Bit 6: RRFEA/B – RSSI Range Fail Enable on Path A/B

Bit 5: TELREA/B – Telegram Length Reached Enable on Path A/B

Bit 4: TMOFEA/B – Time-out Fail Enable on Path A/B

Bit 3: MANFEA/B – Manchester Coding Fail Enable on Path A/B

Bit 2: SYTFEA/B – Symbol Timing Check Fail Enabled on Path A/B

Bit 1: AMPFEA/B – Demodulation Amplitude Check Fail Enable on Path A/B

Bit 0: CARFA/B – Carrier Check Fail Enable on Path A/B

EOT2A, EOT2B

The EOT2A/B variables are a copy of the end of telegram conditions 2 registers (EOTC2A/B) and contain the EOT configuration during SFID check for path A and path B. See RX Telegram Handling for a functional description, and RX DSP Control for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00C8	EOT2A	EOTBFE	RRFEA	TELREA	TMOFEA	MANFEA	SYTFEA	AMPFEA	CARFEA
0x00C9	EOT2B	EOTAFE	RRFEB	TELREB	TMOFEB	MANFEB	SYTFEB	AMPFEB	CARFEB

See EOT1A, EOT1B variables for the bit descriptions.

EOT3A, EOT3B

The EOT3A/B variables are a copy of the end of telegram conditions 3 registers (EOTC3A/B) and contain the EOT configuration during payload reception for path A and path B. See RX Telegram Handling for a functional description, and RX DSP Control for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00CA	EOT3A	EOTBFE	RRFEA	TELREA	TMOFEA	MANFEA	SYTFEA	AMPFEA	CARFEA
0x00CB	EOT3B	EOTAFE	RRFEB	TELREB	TMOFEB	MANFEB	SYTFEB	AMPFEB	CARFEB

See EOT1A, EOT1B variables for the bit descriptions.

FEALR_FEANT

The FEALR_FEANT variable contains the antenna-related settings of the RF front end antenna registers (FEALR and FEANT).


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00CC	FEALR_FEANT	—	—	FEALR.RNGE[1:0]		FEANT.LVLC[3:0]

FEALR_FEANT is always set to 0x00.

FEAT

The FEAT variable is a copy of the RF front end antenna tuning register (FEAT) and contains the initial antenna tuning capacitor settings. See Antenna Tuning for a functional description, and SPDT RF Switch and Automatic Antenna Tuning for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00CD	FEAT	—	—	—	—	ANTN[3:0]

Bits 7..4: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 3..0: ANTN[3:0] – Antenna Tuning Capacitor Setting

Initial value for the automatic antenna tuning or standard value if no antenna tuning is used. The default value is 7.

FEPAC

The FEPAC variable is a copy of the RF front end power amplifier control register (FEPAC) and contains power amplifier current source control settings. See Power Amplifier for a functional description, and Power Amplifier for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00CE	FEPAC	PACR[7:0]

Bits 7..0: PACR[7:0] – Power Amplifier Control

FEVCO

The FEVCO variable is a copy of the RF front end VCO and PLL control register (FEVCO) and contains the front end VCO control settings. See VCO for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00CF	FEVCO	VCOB[3:0]				CPCC[3:0]

Bits 7..4: VCOB[3:0] – VCO Bias

Bits 3..0: CPCC[3:0] – Charge Pump Current Control

FEVCT

The FEVCT variable is a copy of the RF front end VCO tuning register (FEVCT) and contains VCO tuning control settings. See VCO Tuning for a functional description, and VCO for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00D0	FEVCT	—	—	—	—	FEVCT[3:0]

Bits 7..4: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 3..0: FEVCT[3:0] – Front-end VCO Tuning Control Initial value for the VCO tuning. The default value is 7.

FREQoffset

The FREQoffset variable contains the frequency offset for subchanneling. See Subchanneling for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00D1	FREQoffset[0]	FREQoffset[7:0]
0x00D2	FREQoffset[1]	FREQoffset[15:8]

The FREQoffset value can be calculated by the following equation:

F R E Q o f f s e t = r o u n d (\frac{f_{o f f s e t} \times 2^{η}}{f_{X T O}}) ......(5)

f_offset: RF frequency offset between subchannels in Hz (0 Hz to 1,000,000 Hz)

η:

17 for High-Band (836 MHz to 956 MHz)
18 for Low-Band (310 MHz to 477 MHz)

f_XTO: XTO frequency in Hz

txDevA, txDevB

The txDevA/B variables contain the FSK frequency deviation settings for path A and path B (high byte and low byte) in TX mode. See Modulation Settings for a functional description.


Address Service0	Name	Bit 7
0x00D3	txDevA[0]	txDevA[7:0]
0x00D4	txDevA[1]	txDevA[15:8]
0x00D5	txDevB[0]	txDevB[7:0]
0x00D6	txDevB[1]	txDevB[15:8]

The txDevA/B value can be calculated by the following equation:

t x D e v = r o u n d (\frac{2 \times {}^{f}{D e v} \times 2^{η}}{f_{X T O}}) ......(6)

f_Dev: FSK RF frequency deviation (±) in Hz (0.375 kHz to 93 kHz)

η:

17 for High-Band (836 MHz to 956 MHz)
18 for Low-Band (310 MHz to 477 MHz)

f_XTO: XTO frequency in Hz

GACDIVA, GACDIVB

The GACDIVA/B variables are a copy of the Gauss clock divider registers (GACDIVH/L) and contain the Gauss clock divider settings for path A and path B. See General TX Settings for a functional description, and TX DSP for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4
0x00D7	GACDIVA[0]	GACDIVL[7:0]
0x00D8	GACDIVA[1]	—	—	—	GACDIVH[4:0]
0x00D9	GACDIVB[0]	GACDIVL[7:0]
0x00DA	GACDIVB[1]	—	—	—	GACDIVH[4:0]

Note:

GACDIVL[7:0] – Gauss Clock Divider Low Byte
GACDIVH[4:0] – Gauss Clock Divider High Byte

The IF variable contains the intermediate frequency setting.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00DB	IF[0]	IF[7:0]
0x00DC	IF[1]	IF[15:8]

The IF value can be calculated by the following equation:

I F = r o u n d (\frac{F_{R F}}{F_{X T O}} \times \frac{2^{η}}{F_{L O_I F}}) ......(7)

f_RF: RF frequency in Hz

f_XTO: XTO frequency in Hz

η:

17 for High-Band (836 MHz to 956 MHz)
18 for Low-Band (310 MHz to 477 MHz)

FLO_IF:

1225 for Low-Band 310 MHz to 318 MHz
1728 for Low-Band 418 MHz to 477 MHz
3457 for High-Band 836 MHz to 956 MHz

RDOCR

The RDOCR variable contains the receive output control settings. See RXMode(buffered) for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00DD	RDOCR	—	0	0	ETRPB	ETRPA	TMDS[1:0]		—

Bit 7: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 6: Reserved Bit

This bit must always be set to ‘0’.

Bit 5: Reserved Bit

This bit must always be set to ‘0’.

Bit 4: ETRPB – Enable Raw Transparent Output Path B to Pin 19/TRPB

Bit 3: ETRPA – Enable Raw Transparent Output Path A to Pin 16/TRPA

Bits 2..1: TMDS[1:0] – Transparent Mode Data Select

In transparent receive mode, the TMDS bits are irrelevant because the data selection is done by the firmware and the SSM. In buffered receive mode, an additional reshaped transparent output on the 17/TMDO and 19/TMDO_CLOCK pins is activated if at least one of the TMDS bits is set to ‘1’. The active path is automatically selected by the SSM.

Bit 0: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

rssiSysConf

The rssiSysConf variable is used for RSSI enabling/disabling and event signaling. See RSSI Measurement for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00DE	rssiSysConf	RssiEnable	—	rssiBufEvMask	RSSIbuf[4:0]

Bit 7: RssiEnable – RSSI Enable

0 = RSSI disabled

1 = RSSI enabled

Bit 6: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 5: rssiBufEvMask – SFIFO Fill Level Event Mask in Receive Mode

0 = No external event on pin 28 (EVENT) is generated if the SFIFO fill level is reached

1 = An external event on pin 28 (EVENT) is generated if the SFIFO fill level is reached

Bits 4..0: RSSIbuf[4:0] – SFIFO [4:0] Fill Level Threshold in Receive Mode

rxSetPathA[0], rxSetPathB[0]

The rxSetPathA/B[0] variables are used for RX event signaling and configuration for path A/B. See RXMode(buffered) for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00DF	rxSetPathA[0]	—	rxBufEvMaskA	RXbufA[5:0]
0x00E1	rxSetPathB[0]	—	rxBufEvMaskB	RXbufB[5:0]

Bit 7: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 6: rxBufEvMaskA/B – DFIFO Fill Level Path A/B in Receive Mode

0 = No external event on pin 28 (EVENT) is generated if the DFIFO fill level on path A/B is reached in receive mode.

1 = An external event on pin 28 (EVENT) is generated if the DFIFO fill level on path A/B is reached in receive mode.

Bits 5..0: RXbufA/B[5:0] – DFIFO A/B [5:0] Fill Level Threshold in Receive Mode

rxSetPathA[1], rxSetPathB[1]

The rxSetPathA/B[1] variables are mainly used for RX telegram handling control for path A and path B. See RX Telegram Handling for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00E0	rxSetPathA[1]	IWUPA	DARA	GAPMA	RXTEHA	—	—	—	RXMODA
0x00E2	rxSetPathB[1]	IWUPB	DARB	GAPMB	RXTEHB	—	—	—	RXMODB

Bit 7: IWUPA/B – Intermittent WUP Path A/B

0 = Intermittent WUP disabled

1 = Intermittent WUP enabled

Bit 6: DARA/B – Demodulator Automatic Restart on Path A/B

0 = Demodulator automatic restart disabled

1 = Demodulator automatic restart enabled

Bit 5: GAPMA/B – Gap Mode Path A/B

0 = Gap mode disabled

1 = Gap mode enabled

Bit 4: RXTEHA/B – RX Telegram End Handling Path A/B

0 = Return to IDLEMode after EOT

1 = Stay in RxMode after EOT

Bits 3..1: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 0: RXMODA/B – RX Modulation Path A/B

0 = FSK modulation

1 = ASK modulation

rxSysEvent

The rxSysEvent variable contains the configuration masks for the system events. For a functional description, see Event Handling.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00E3	rxSysEvent	IDCHKA_Mask	WCOKA_Mask	SOTA_Mask	EOTA_Mask	IDCHKB_Mask	WCOKB_Mask	SOTB_Mask	EOTB_Mask

Bit 7: IDCHKA_Mask – ID Check OK on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if ID check OK on path A

1 = An external event on pin 28 (EVENT) is generated if ID check OK on path A

Bit 6: WCOKA_Mask – Wake Check OK on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if wake check OK on path A

1 = An external event on pin 28 (EVENT) is generated if wake check OK on path A

Bit 5: SOTA_Mask – Start of Telegram on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if SOT on path A

1 = An external event on pin 28 (EVENT) is generated if SOT on path A

Bit 4: EOTA_Mask – End of Telegram on Path A Mask

0 = No external event on pin 28 (EVENT) is generated if EOT on path A

1 = An external event on pin 28 (EVENT) is generated if EOT on path A

Bit 3: IDCHKB_Mask – ID Check OK on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if ID check OK on path B

1 = An external event on pin 28 (EVENT) is generated if ID check OK on path B

Bit 2: WCOKB_Mask – Wake Check OK on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if wake check OK on path B

1 = An external event on pin 28 (EVENT) is generated if wake check OK on path B

Bit 1: SOTB_Mask – Start of Telegram on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if SOT on path B

1 = An external event on pin 28 (EVENT) is generated if SOT on path B

Bit 0: EOTB_Mask – End of Telegram on Path B Mask

0 = No external event on pin 28 (EVENT) is generated if EOT on path A

1 = An external event on pin 28 (EVENT) is generated if EOT on path A

rxSysSet

The rxSysSet variable is used for enabling and disabling various RXMode features. See General RX Settings for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00E4	rxSysSet	subChanneling_ENA	IdScan_ENA	IFAmplifier_ENA	PathValidAfterSOT_ENA	AntennaDampingPathB _DIS	AntennaDampingPathA _DIS	switching _SDTX	switching _SDRX

Bit 7: subChanneling_ENA – Subchanneling Enable

0 = Disable subchanneling

1 = Enable subchanneling

Bit 6: IdScan_ENA – ID Check Enable

0 = Disable ID check

1 = Enable ID check

Bit 5: IFAmplifier_ENA – IF Amplifier Enable

This bit must always be set to ‘1’ during normal operation.

Bit 4: PathValidAfterSOT_ENA – Path Valid after Start of Telegram Enable

0 = Path valid after SOT disable

1 = Path valid after SOT enable

Bit 3: AntennaDampingPathA_DIS – Antenna Damping on Path A Disable

0 = Enable antenna damping on path A

1 = Disable antenna damping on path A

Bit 2: AntennaDampingPathB_DIS – Antenna Damping on Path B Disable

0 = Enable antenna damping on path B

1 = Disable antenna damping on path B

Bit 1: switching_SDTX – Antenna Switching to Pin 6

0 = Disable pin 6 as SPDT switch input

1 = Enable pin 6 as SPDT switch input

Bit 0: switching_SDRX – Antenna Switching to Pin 3

0 = Disable pin 3 as SPDT switch input

1 = Enable pin 3 as SPDT switch input

SFIDA, SFIDB

The SFIDA/B[3:0] variables are a copy of the start frame ID A/B registers (SFID[4:1]A/B) and contain the start frame ID pattern for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Frame Synchronizer for a hardware description.


Address Service0	Name	Bit 7
0x00E5	SFIDA[0]	SFID1A[7:0]
0x00E6	SFIDA[1]	SFID2A[7:0]
0x00E7	SFIDA[2]	SFID3A[7:0]
0x00E8	SFIDA[3]	SFID4A[7:0]
0x00E9	SFIDB[0]	SFID1B[7:0]
0x00EA	SFIDB[1]	SFID2B[7:0]
0x00EB	SFIDB[2]	SFID3B[7:0]
0x00EC	SFIDB[3]	SFID4B[7:0]

SFIDCA, SFIDCB

The SFICA/B variables are a copy of the start frame ID configuration registers (SFIDCA/B) and contain the start frame ID configuration for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Frame Synchronizer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00ED	SFIDCA	SEMEA	—	—	SFIDTA[4:0]
0x00EE	SFIDCB	SEMEB	—	—	SFIDTB[4:0]

Bit 7: SEMEA/B – Serial Mode Enable for Path A/B

0 = Serial Mode Disabled

1 = Serial Mode Enabled

Bits 6..5: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 4..0: SFIDTA/B[4:0] – SFID Threshold for Path A/B

SFIDLA, SFIDLB

The SFIDLA/B variables are a copy of the start frame ID length registers (SFIDLA/B) and contain the start frame ID length settings for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Frame Synchronizer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00EF	SFIDLA	—	—	SFIDLA[5:0]
0x00F0	SFIDLB	—	—	SFIDLB[5:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 5..0: SFIDLA/B[5:0] – SFID Length for Path A/B (0..32)

SOT1A, SOT1B

The SOT1A/B variables are a copy of the start of telegram conditions 1 registers (SOTC1A/B) and contain the SOT configuration during WUP check for path A and path B. See RX Telegram Handling for a functional description, and RX DSP Control for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00F1	SOT1A	WCOBOE	RROEA	SFIDEA	WUPEA	MANOEA	SYTOEA	AMPOEA	CAROEA
0x00F2	SOT1B	WCOAOE	RROEB	SFIDEB	WUPEB	MANOEB	SYTOEB	AMPOEB	CAROEB

Bit 7: WCOB/AOE – Wake Check OK from Path B/A OK Enable

Bit 6: RROEA/B – RSSI Range OK Enable for Path A/B

Bit 5: SFIDEA/B – SFID Match Enable for Path A/B

Bit 4: WUPEA/B – Wake Up Pattern Match Enable for Path A/B

Bit 3: MANOEA/B – Manchester Coding OK Enable for Path A/B

Bit 2: SYTOEA/B – Symbol Timing Check OK Enable for Path A/B

Bit 1: AMPOEA/B – Demodulation Amplitude Check OK Enable for Path A/B

Bit 0: CAROEA/B – Carrier Check OK Enable for Path A/B

SOT2A, SOT2B

The SOT2A/B variables are a copy of the start of telegram conditions 2 registers (SOTC2A/B) and contain the SOT configuration during SOT check for path A and path B. See RX Telegram Handling for a functional description, and RX DSP Control for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00F3	SOT2A	WCOBOE	RROEA	SFIDEA	WUPEA	MANOEA	SYTOEA	AMPOEA	CAROEA
0x00F4	SOT2B	WCOAOE	RROEB	SFIDEB	WUPEB	MANOEB	SYTOEB	AMPOEB	CAROEB

See SOT1A, SOT1B variables for the bit descriptions.

SOTtimeOutA, SOTtimeOutB

The SOTtimeOutA/B variables are a copy of the SOT OK time-out for path A/B registers (SOTTOA/B) and contain the start of telegram time-out configuration for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Sequencer State Machine for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00F5	SOTtimeOutA	SOTTOA[7:0]
0x00F6	SOTtimeOutB	SOTTOB[7:0]

Bits 7..0: SOTTOA/B[7:0] – SOT Time-out for Path A/B

SOTTOA/B allows setting time-out periods between approximately 5 µs and 300 ms. A precise formula is given at the corresponding hardware register description.

SYCA, SYCB

The SYCA/B variables are a copy of the symbol check configuration registers (SYCA/B) and contain the symbol check configuration for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Demodulator and Signal Checks for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00F7	SYCA	SYTLA[3:0]				SYCSA[3:0]
0x00F8	SYCB	SYTLB[3:0]				SYCSB[3:0]

Bits 7..4: SYTLA/B[3:0] – Symbol Timing Limit for Path A/B

Bits 3..0: SYCSA/B[3:0] – Symbol Check Size for Path A/B

FSFCRA, FSFCRB

The FSFRCA/B variables are a copy of the frequency synthesizer filter control register (FSFCR) and contain the TX DSP filter control settings for path A and path B. See TX Filtering for a functional description, and TX DSP for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00F9	FSFCRA	ASDIV[3:0]				—	—	BTSEL[1:0]
0x00FA	FSFCRB	ASDIV[3:0]				—	—	BTSEL[1:0]

Bits 7..4: ASDIV[3:0] – ASK Shaping Divider Value for Path A/B

Bits 3..2: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 1..0: BTSEL[1:0] – Gaussian Shaping Filter Bit-time-Bandwidth-Product Selection for Path A/B

TMUL

The TMUL variable contains the multiplier to calculate temperature compensation of the crystal. See RF Calibration for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00FB	TMUL	TMUL[7:0]

The TMUL value can be calculated by the following equation:

T M U L = r o u n d (32 \times f_{R F} / (10^{6} \times f_{S T E P})) ......(8)

f_RF: RF channel frequency

f_Step= f_XTO / (N x 2¹⁶)

f_XTO: Crystal oscillator frequency

N = 4 for Low-Band (315 MHz/433 MHz)

N = 2 for High-Band (868 MHz/915 MHz)

trxSysConf

The trxSysConf variable contains the enable bits for antenna switching and channel switching. See General RX Settings for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x00FC	trxSysConf	—	—	—	—	TRPB_ENA	TRPA_ENA	AntennaSwitching_ENA	ChannelSwitch_ENA

Bits 7..4: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 3: TRPB_ENA – Transparent RX Path B Enable

This setting is not used by the ATA8510/15 firmware. Use eepServices.RDOCR.ETRPB to activate the raw transparent output on path B.

Bit 2: TRPA_ENA – Transparent RX Path A Enable

This setting is not used by the ATA8510/15 firmware. Use eepServices.RDOCR.ETRPA to activate the raw transparent output on path A.

Bit 1: AntennaSwitching_ENA – Antenna Switching Enable

0 = Disable antenna switching

1 = Enable antenna switching

Bit 0: ChannelSwitch_ENA – Channel Switch Control Enable

0 = Disable channel switch control

1 = Enable channel switch control

TXDRA, TXDRB

The TXDRA/B variables contain the TX data rate settings of path A and path B. The configurations are used for firmware calculations. See General TX Settings for a functional description.


Address Service0	Name	Bit 7
0x00FD	TXDRA[0]	TXDRA[7:0]
0x00FE	TXDRA[1]	TXDRA[15:8]
0x00FF	TXDRB[0]	TXDRB[7:0]
0x0100	TXDRB[1]	TXDRB[15:8]

Bits 7..0: TXDRA/B[15:0] – TX Data Rate Setting for Path A/B

TXDRA/B is the compare value the Timer3 that generates the TX data rate and can be calculated by the following formula:

T X D R x = r o u n d (\frac{F_{X T O}}{4 \times F_{s y m}}) ......(9)

F_XTO: XTO frequency in Hz

F_sym: Symbol rate in Hz

txSetPathA[0], txSetPathB[0]

The txSetPathA/B[0] variables contain the TXMode configuration of path A and path B. See Data Transmission for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0101	txSetPathA[0]	GAUS	PREE	StartTxFillLevelA[5:0]
0x0103	txSetPathB[0]	GAUS	PREE	StartTxFillLevelB[5:0]

Bit 7: GAUS – Gauss Enable

0 = Disable Gaussian shaping filter for TX

1 = Enable Gaussian shaping filter for TX

Bit 6: PREE – Pre-emphasis Enable

0 = Disable pre-emphasis filter for TX

1 = Enable pre-emphasis filter for TX

Bits 5..0: StartTxFillLevelA/B[5:0] – Fill Level Threshold of DFIFO to Start Transmission

txSetPathA[1], txSetPathB[1]

The txSetPathA/B[1] variables contain the TXMode configuration of path A and path B. See Data Transmission for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0102	txSetPathA[1]	TXMODA	ASKshapingenable	—	StartPreambleFillLevelA[4:0]
0x0104	txSetPathB[1]	TXMODB	ASKshapingenable	—	StartPreambleFillLevelB[4:0]

Bit 7: TXMODA/B – TX Modulation Path A/B

0 = FSK modulation

1 = ASK modulation

Bit 6: ASKshapingenable – ASK Shaping enabled for Path A/B

0 = Disable ASK shaping filter for path A/B

1 = Enable ASK shaping filter for path A/B

Bit 5: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bits 4..0: StartPreambleFillLevelA/B[4:0] – Fill Level Threshold of SFIFO to Start Transmission

txSysEventA, txSysEventB

The txSysEventA/B variables contain the event configuration in TXMode for transmission on path A and path B. See Event Handling for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0105	txSysEventA	TX_Ending	txBufEvMaskA	TxBufFillLevelA[5:0]
0x0106	txSysEventB	TX_Ending	txBufEvMaskB	TxBufFillLevelB[5:0]

Bit 7: TX_Ending – Behavior after Transmission Completion

0 = Go to IDLEMode

1 = Stay in TXMode, PA OFF

Bit 6: txBufEvMaskA/B – DFIFO Fill Level Path A/B in Transmit Mode

0 = No external event on pin 28 (EVENT) is generated if the DFIFO fill level on path A/B is reached in transmit mode

1 = An external event on pin 28 (EVENT) is generated if the DFIFO fill level on path A/B is reached in transmit mode

Bits 5..0: TxBufFillLevelA/B[5:0] – Fill Level Threshold of DFIFO in TXMode

txPreambleSysEventA, txPreambleSysEventB

The txPreambleSysEventA/B variables contain the event configuration in TXMode for transmission on path A and path B. See Event Handling for a functional description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0107	txPreambleSysEventA	—	—	txPreambleBufEvMaskA	PreambleBufFillLevelA[4:0]
0x0108	txPreambleSysEventB	—	—	txPreambleBufEvMaskB	PreambleBufFillLevelB[4:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: txPreambleBufEvMaskA/B – SFIFO Event Mask for Path A/B in Transmit Mode

0 = No external event on pin 28 (EVENT) is generated if the SFIFO fill level on path A/B is reached in transmit mode

1 = External event on pin 28 (EVENT) is generated if the SFIFO fill level on path A/B is reached in transmit mode

Bits 4..0: PreambleBufFillLevelA/B[4:0] – Fill Level Threshold of SFIFO in TXMode

WCOtimeOutA, WCOtimeOutB

The WCOtimeOutA/B variables are a copy of the WCO time-out for path A/B registers (WCOTOA/B) and contain the wake check OK time-out configuration for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Sequencer State Machine for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0109	WCOtimeOutA	WCOTOA[7:0]
0x010A	WCOtimeOutB	WCOTOB[7:0]

Bits 7..0: WCOTOA/B[7:0] – WCO Time-out for Path A/B

WCOTOA/B allows time-out periods to be set between approximately 5 µs and 300 ms. A precise formula is given at the corresponding hardware register description.

WUPA, WUPB

The WUPA/B[3:0] variables are a copy of the wake-up pattern A/B registers (WUP[4:1]A/B) and contain the wake-up pattern for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Frame Synchronizer for a hardware description.


Address Service0	Name	Bit 7
0x010B	WUPA[0]	WUP1A[7:0]
0x010C	WUPA[1]	WUP2A[7:0]
0x010D	WUPA[2]	WUP3A[7:0]
0x010E	WUPA[3]	WUP4A[7:0]
0x010F	WUPB[0]	WUP1B[7:0]
0x0110	WUPB[1]	WUP2B[7:0]
0x0111	WUPB[2]	WUP3B[7:0]
0x0112	WUPB[3]	WUP4B[7:0]

WUPLA, WUPLB

The WUPLA/B variables are a copy of the wake-up pattern length registers (WUPLA/B) and contain the wake-up pattern length settings for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Frame Synchronizer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0113	WUPLA	—	—	WUPLA[5:0]
0x0114	WUPLB	—	—	WUPLB[5:0]

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 5..0: WUPLA/B[5:0] – WUP Length for Path A/B (0..32)

WUPTA, WUPTB

The WUPTA/B variables are a copy of the wake-up pattern threshold registers (WUPTA/B) and contain the wake-up pattern threshold for path A and path B. See Telegram Settings and Signal Checks for a functional description, and Frame Synchronizer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0115	WUPTA	—	—	—	WUPTA[4:0]
0x0116	WUPTB	—	—	—	WUPTB[4:0]

Bits 7..5: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bits 4..0: WUPTA/B[4:0] – WUP Threshold for Path A/B

RXCPA[1:0], RXCPB[1:0]

The RXCPA/B[1:0] variables are a copy of the RX CRC polynomial registers (RXCPHA/B and RXCPLA/B) and contain the RX CRC polynomial for path A and path B. See Receive CRC Checker for a functional description, and RX Buffer for a hardware description.


Address Service0	Name	Bit 7
0x0117	RXCPA[0]	RXCPLA[7:0]
0x0118	RXCPA[1]	RXCPHA[7:0]
0x011E	RXCPB[0]	RXCPLB[7:0]
0x011F	RXCPB[1]	RXCPHB[7:0]

Bits 7..0: RXCPLA/B[7:0] – RX CRC Polynomial Low Byte for Path A/B

Bits 7..0: RXCPHA/B[7:0] – RX CRC Polynomial High Byte for Path A/B

RXCIA[1:0], RXCIB[1:0]

The RXCIA/B[1:0] variables are a copy of the RX CRC initialization registers (RXCIHA/B and RXCILA/B) and contain the RX CRC initialization value for path A and path B. See Receive CRC Checker for a functional description, and RX Buffer for a hardware description.


Address Service0	Name	Bit 7
0x0119	RXCIA[0]	RXCILA[7:0]
0x011A	RXCIA[1]	RXCIHA[7:0]
0x0120	RXCIB[0]	RXCILB[7:0]
0x0121	RXCIB[1]	RXCIHB[7:0]

Bits 7..0: RXCILA/B[7:0] – RX CRC Init Value Low Byte for Path A/B

Bits 7..0: RXCIHA/B[7:0] – RX CRC Init Value High Byte for Path A/B

RXCSBA, RXCSBB

The RXCSBA/B variables are a copy of the RX CRC skip bits registers (RXCSBA/B) and contain the RX CRC skip bits value for path A and path B. See Receive CRC Checker for a functional description, and RX Buffer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x011B	RXCSBA	RXCSBA[7:0]
0x0122	RXCSBB	RXCSBB[7:0]

Bits 7..0: RXCSBA/B[7:0] – RX CRC Skip Bit Number for Path A/B

RXTLA[1:0], RXTLB[1:0]

The RXTLA/B[1:0] variables are a copy of the RX telegram length registers (RXTLHA/B and RXTLLA/B) and contain the telegram length setting in RXMode(buffered) for path A and path B. See Telegram Settings and Signal Checks for a functional description, and RX Buffer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3
0x011C	RXTLA[0]	RXTLLA[7:0]
0x011D	RXTLA[1]	—	—	—	—	RXTLHA[3:0]
0x0123	RXTLB[0]	RXTLLB[7:0]
0x0124	RXTLB[1]	—	—	—	—	RXTLHB[3:0]

Bits 7..0: RXTLLA/B[7:0] – RX Telegram Length Low Byte for Path A/B

Bits 3..0: RXTLHA/B[3:0] – RX Telegram Length High Byte for Path A/B

RXBC1

The RXBC1 variable is a copy of the RX buffer control 1 register (RXBC1) and contains the settings for the RX buffer configuration for path A and path B. See General RX Settings for a functional description, and RX Buffer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0125	RXBC1	RXMSBB	RXCBLB[1:0]		RXCEB	RXMSBA	RXCBLA[1:0]		RXCEA

Bit 7: RXMSBB – RX MSB-First for Path B

Bits 6..5: RXCBLB[1:0] – RX CRC Bit Length for Path B

Bit 4: RXCEB – RX CRC Enable for Path B

Bit 3: RXMSBA – RX MSB-First for Path A

Bits 2..1: RXCBLA[1:0] – RX CRC Bit Length for Path A

Bit 0: RXCEA – RX CRC Enable for Path A

TMCR2A, TMCR2B

The TMCR2A/2B variables are a copy of the TX modulator control register 2 (TMCR2) and contain the TX modulator control settings for path A and path B. See TXMode (buffered) for a functional description, and TX Modulator for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0126	TMCR2A	—	TMMSB	TMSSE	TMPOL	TMNRZE	TMCRCL[1:0]		TMCRCE
0x0127	TMCR2B	—	TMMSB	TMSSE	TMPOL	TMNRZE	TMCRCL[1:0]		TMCRCE

Bit 7: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 6: TMMSB – TX Modulator MSB-First

Bit 5: TMSSE – TX Modulator Stop Sequence Enable

Bit 4: TMPOL – TX Modulator Polarity

Bit 3: TMNRZE – TX Modulator NRZ Mode Enable

Bits 2..1: TMCRCL[1:0] – TX Modulator CRC Length

Bit 0: TMCRCE – TX Modulator CRC Enable

TMSSCA, TMSSCB

The TMSSCA/B variables are a copy of the TX modulator stop sequence configuration register (TMSSC) and contain the stop sequence configuration for path A and path B. See TXMode (buffered) for a functional description, and TX Modulator for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0128	TMSSCA	TMSSH	TMSSL[2:0]			TMSSP[3:0]
0x0129	TMSSCB	TMSSH	TMSSL[2:0]			TMSSP[3:0]

Bit 7: TMSSH – TX Modulator Stop Sequence Hold Mode

Bits 6..4: TMSSL[2:0] – TX Modulator Stop Sequence Length

Bits 3..0: TMSSP[3:0] – TX Modulator Stop Sequence Pattern

TMTLA[1:0], TMTLB[1:0]

The TMTLA/B variables are a copy of the TX modulator telegram length registers (TMTLH and TMTLL) and contain the TX telegram length configuration for path A and path B. See TXMode (buffered) for a functional description, and TX Modulator for a hardware description.


Address Service0	Name	Bit 7
0x012A	TMTLA[0]	TMTLL[7:0]
0x012B	TMTLA[1]	TMTLH[7:0]
0x012C	TMTLB[0]	TMTLL[7:0]
0x012D	TMTLB[1]	TMTLH[7:0]

Bits 7..0: TMTLL[7:0] – TX Modulator Telegram Length Low Byte

Bits 7..0: TMTLH[7:0] – TX Modulator Telegram Length High Byte

TMCPA[1:0], TMCPB[1:0]

The TMCPA/B variables are a copy of the TX modulator CRC polynomial registers (TMCPH and TMCPL) and contain the TX CRC polynomial for path A and path B. See TXMode (buffered) for a functional description, and TX Modulator for a hardware description.


Address Service0	Name	Bit 7
0x012E	TMCPA[0]	TMCPL[7:0]
0x012F	TMCPA[1]	TMCPH[7:0]
0x0130	TMCPB[0]	TMCPL[7:0]
0x0131	TMCPB[1]	TMCPH[7:0]

Bits 7..0: TMCPL[7:0] – TX Modulator CRC Polynomial Low Byte

Bits 7..0: TMCPH[7:0] – TX Modulator CRC Polynomial High Byte

TMCIA[1:0], TMCIB[1:0]

The TMCIA/B variables are a copy of the TX modulator CRC init registers (TMCIH and TMCIL) and contain the TX CRC initialization value for path A and path B. See TXMode (buffered) for a functional description, and TX Modulator for a hardware description.


Address Service0	Name	Bit 7
0x0132	TMCIA[0]	TMCIL[7:0]
0x0133	TMCIA[1]	TMCIH[7:0]
0x0134	TMCIB[0]	TMCIL[7:0]
0x0135	TMCIB[1]	TMCIH[7:0]

Bits 7..0: TMCIL[7:0] – TX Modulator CRC Initialization Low Byte

Bits 7..0: TMCIH[7:0] – TX Modulator CRC Initialization High Byte

TMCSBA, TMCSBB

The TMCSBA/B variables are a copy of the TX modulator CRC skip bit number register (TMCSB) and contain the number of TX CRC skip bits for path A and path B. See TXMode (buffered) for a functional description, and TX Modulator for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0136	TMCSBA	TMCSB[7:0]
0x0137	TMCSBB	TMCSB[7:0]

Bits 7..0: TMCSB [7:0] – TX Modulator CRC Skip Bit Number

RSSC

The RSSC variable is a copy of the receive signal strength configuration register (RSSC) and contains the control settings of the RSSI buffer. See RSSI Measurement for a functional description, and RSSI Buffer for a hardware description.


Address Service0	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x0138	RSSC	—	RSPKF	RSHRX	RSWLH	RSUP[3:0]

Bit 7: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 6: RSPKF – RSSI Peak Values to SFIFO

Bit 5: RSHRX – RSSI High Band Reception

Bit 4: RSWLH – RSSI Within Low and High Limits

Bits 3..0: RSUP[3:0] – RSSI Update Period