3.10.7.5.1.1 T4CR – Timer 4 Control Register


Bit	7	6	5	4	3	2	1	0
	T4ENA	T4TOS	T4RES	T4TOP	T4CPRM	T4CRM	T4CTM	T4OTM
Access	R/W	R/W	W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – T4ENA Timer4 Enable

This bit controls the Timer4 block. The T4ENA bit must be written to logic ‘1’ to enable Timer4. If the T4ENA bit is written to logic ‘0’, Timer4 is disabled. Reading this bit shows the actual state of Timer4. Because internal synchronization requires 2½ asynchronous CL4 clock cycles to enable or disable Timer4, it may take some time to read a logic ‘1’ after having enabled Timer4. The same applies for disabling.

Bit 6 – T4TOS Timer4 Toggle with Start

The T4TOS bit must be written to logic ‘1’ if the modulator output of Timer4 must toggle when the timer is enabled with T4ENA. If the T4TOS bit is written to logic ‘0’, the modulator output of Timer4 is not toggled on timer enable.

Bit 5 – T4RES Timer4 Reset

The T4RES bit can be written to logic ‘1’ to reset the prescaler and counter. This is only allowed if the timer is stopped (T4ENA = 0). The T4RES bit is automatically cleared one cycle after the write.

Bit 4 – T4TOP T4 Toggle Output Preset

The T4TOP bit must be written to logic ‘1’ to set the toggle flip-flop. If the T4TOP bit is written to logic ‘0’, it resets the toggle flip-flop. This bit allows the programmer to preset the toggle output flip-flop in the modulator of Timer4.

Note: If T4ENA = 1, no output preset is possible.

Bit 3 – T4CPRM Timer4 Capture Reset Mask

The T4CPRM bit must be written to logic ‘1’ to enable the counter reset if an internal/external capture event occurs. If the T4CPRM bit is written to logic ‘0’, the counter reset is disabled.

Bit 2 – T4CRM Timer4 Compare Reset Mask

The T4CRM bit must be written to logic ‘1’ to enable the counter reset if a match of the counter with the compare register (T4COR) occurs. If the T4CRM bit is written to logic ‘0’, the counter reset is disabled.

Bit 1 – T4CTM Timer4 Compare Toggle Mask

The T4CTM bit must be written to logic ‘1’ to enable the compare toggle. A match of the counter with the compare register (T4COR) toggles the output flip-flop in the modulator of Timer4. If the T4CTM bit is written to logic ‘0’, the compare toggle is disabled.

Bit 0 – T4OTM Timer4 Overflow Toggle Mask

The T4OTM bit must be written to logic ‘1’ to enable the overflow toggle. A counter overflow generates an output clock of the counter (CLK_T4). If the T4OTM bit is written to logic ‘0’, the overflow toggle is disabled.

Name:	T4CR
Offset:	0x014
Reset:	0x00