3.10.7.5.1.2 T4MRA – Timer4
Mode Register A
| Name: | T4MRA |
| Offset: | 0x086 |
| Reset: | 0x00 |
This register must
be modified only while the timer is disabled (T4CR.T4ENA = 0).
Modifying the bits during operation leads to unpredictable
operation.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | T4PS[2:0] | T4CS[1:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bits 4:2 – T4PS[2:0] Timer 4 Prescaler Select
The T4PS[2:0] bits select the
prescaler value of Timer4 as shown in the following table.
Table 3-98. Timer 4 Prescaler
Value Select Bit Description| T4PS[2:0] | Prescaler Value |
|---|
0 | 0 | 0 | 1 |
0 | 0 | 1 | 2 |
0 | 1 | 0 | 4 |
0 | 1 | 1 | 8 |
1 | 0 | 0 | 16 |
1 | 0 | 1 | 32 |
1 | 1 | 0 | 64 |
1 | 1 | 1 | Reserved |
Bits 1:0 – T4CS[1:0] Timer 4 Clock Select
The T4CS[1:0] bits select the
input clock (CL4) of Timer4 as shown in the following table.
Table 3-99. Timer4 Input Clock
Select Bit Description| T4CS[1:0] | Input Clock (CL4) of the Prescaler |
|---|
0 | 0 | CLKSRC |
0 | 1 | CLKT |
1 | 0 | CLKXTO6 |
1 | 1 | CLKFRC |
