3.10.7.5.1.4 T4IFR – Timer4
Interrupt Flag Register
| Name: | T4IFR |
| Offset: | 0x018 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | T4ICF | T4COF | T4OFF | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – T4ICF Timer4 Input
Capture Flag
This flag is set when a
capture event occurs on the selected capture source, indicating that the counter
value was transferred to the capture register (T4ICR). If the I bit in SREG and the
T4CPIM bit in T4IMR register are set, the MCU jumps to the corresponding interrupt
vector. T4ICF is automatically cleared when the interrupt routine is executed.
Alternatively, T4ICF can be cleared by writing a logic ‘1’ to this
bit location.
Bit 1 – T4COF Timer4 Compare
Flag
This flag is set during the
clock cycle after the Timer4 counter value has matched with the compare register. If
the I bit in SREG and the T4CIM bit in the T4IMR register are set, the MCU jumps to
the corresponding interrupt vector. The flag (T4COF) is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical
‘1’ to it.
Bit 0 – T4OFF Timer4 Overflow
Flag
This flag is set by the T4OVF
signal when the counter reaches its maximum value (0xFFFF). If the I bit in SREG and
the T4OIM bit in the T4IMR register are set, the MCU jumps to the corresponding
interrupt vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical ‘1’ to
it.
