3.10.7.5.1.5 T4IMR – Timer4
Interrupt Mask Register
| Name: | T4IMR |
| Offset: | 0x088 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | T4CPIM | T4CIM | T4OIM | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – T4CPIM Timer4 Capture
Interrupt Mask
If this bit is written to
‘1’ and the I flag in SREG is set (interrupts globally
enabled), the Timer4 input capture interrupt is enabled. The corresponding interrupt
vector is executed when the T4ICF Flag, located in T4IFR, is
set.
Bit 1 – T4CIM Timer4 Compare
Interrupt Mask
If the T4CIM bit is written to
‘1’ and the I bit in SREG is set, the Timer4 compare match
interrupt is enabled. The corresponding interrupt is executed if a compare match in
Timer4 occurs, and when the T4COF bit is set in the Timer4 interrupt flag register
(T4IFR).
Bit 0 – T4OIM Timer4 Overflow
Interrupt Mask
If the T4OIM bit is written to
‘1’ and the I bit in SREG is set, the Timer4 overflow interrupt
is enabled. The corresponding interrupt is executed if an overflow in Timer4 occurs,
and when the T4OFF bit is set in the Timer4 interrupt flag register
(T4IFR).
