3.4.3.3.1.12 SFIDCA – Start Frame ID Configuration for Path A

Name: SFIDCA
Offset: 0x0B7
Reset: 0x00

Bit 76543210 
 SEMEASFIDTA[4:0] 
Access R/WRRR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – SEMEA Serial Mode Enable for Path A

Setting this bit to ‘1’ enables a hardware-controlled serial mode for the path A correlator.
ValueDescription
0Parallel search for wake-up pattern (WUP) and start frame ID (SFID) is enabled.
1Serial search for wake-up pattern (WUP) and start frame ID (SFID) is enabled. An SFID match is accepted only after a successful wake-up pattern match.

Bit 6 –  Reserved Bit

This bit is reserved and returns ‘0’ when read.

Bit 5 –  Reserved Bit

This bit is reserved and returns ‘0’ when read.

Bits 4:0 – SFIDTA[4:0] Start Frame ID Threshold for Path A

The number of symbols matching the expected start frame ID has to exceed the number specified in this register to generate a start frame ID OK event (SOTSA.SFIDOA).