46.16 Fractional Digital Phase Locked Loop (FDPLL96M) Electrical Specifications
| AC CHARACTERISTICS | Standard Operating
Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial |
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| Param. No. | Symbol | Characteristics | Min. | Typ. | Max. | Units | Conditions |
| FDPLL96M (Fractional Digital Phase Locked Loop) | |||||||
| FDPLL_1 | FDPLL_FIN | FDPLL96M Input Frequency Range | 32 | — | 2000 | kHz | Over full voltage and temperature
operating ranges. XOSC32 32.768 kHz PPM≤100. XOSC 2 MHz PPM≤100. |
| FDPLL_3 | FDPLL_FOUT | FDPLL96M DCO Output Clock Frequency | 48 | — | 96 | MHz | |
| FDPLL_5 | FDPLL_Jitter | FDPLL96M Period Jitter Pk-to-Pk (1,2) | 1.4 | — | 3.6 | % | VDD = VDDIO = 5.0V, fIN = 32.768 kHz from XOSC32K, fOUT = 48MHz |
| 1 | — | 8.6 | % | VDD = VDDIO = 5.0V, fIN = 32.768 kHz from XOSC32K, fOUT = 96MHz |
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| FDPLL_7 | 1.4 | — | 3.9 | % | VDD = VDDIO = 5.0V, fIN = 2 MHz from XOSC, fOUT = 48MHz |
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| 1 | — | 6.8 | % | VDD = VDDIO = 5.0V, fIN = 2 MHz from XOSC, fOUT = 96MHz |
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| FDPLL_11 | FDPLL_SRT | FDPLL96M Start-Up / Lock Time Time (1) | — | 1.1 | — | ms | VDD = VDDIO = 5.0V, fIN = 32.768 kHz from XOSC32K, fOUT = 96MHz |
| — | 25 | — | µs | VDD = VDDIO = 5.0V, fIN = 2 MHz from XOSC, fOUT = 96MHz |
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Note:
- REFCLK for FDPLL96M is XOSC or XOSC32K.
- DPLL jitter is sensitive to digital on-chip activity, which is application dependent.