46.16 Fractional Digital Phase Locked Loop (FDPLL96M) Electrical Specifications

Table 46-18. Fractional Digital Phase Locked Loop (FDPLL96M) Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
FDPLL96M (Fractional Digital Phase Locked Loop)
FDPLL_1	FDPLL_FIN	FDPLL96M Input Frequency Range	32	—	2000	kHz	Over full voltage and temperature operating ranges. XOSC32 32.768 kHz PPM≤100. XOSC 2 MHz PPM≤100.
FDPLL_3	FDPLL_FOUT	FDPLL96M DCO Output Clock Frequency	48	—	96	MHz
FDPLL_5	FDPLL_Jitter	FDPLL96M Period Jitter Pk-to-Pk ^(1,2)	1.4	—	3.6	%	VDD = VDDIO = 5.0V, f_IN = 32.768 kHz from XOSC32K, f_OUT = 48MHz
FDPLL_5			1	—	8.6	%	VDD = VDDIO = 5.0V, f_IN = 32.768 kHz from XOSC32K, f_OUT = 96MHz
FDPLL_7			1.4	—	3.9	%	VDD = VDDIO = 5.0V, f_IN = 2 MHz from XOSC, f_OUT = 48MHz
FDPLL_7			1	—	6.8	%	VDD = VDDIO = 5.0V, f_IN = 2 MHz from XOSC, f_OUT = 96MHz
FDPLL_11	FDPLL_SRT	FDPLL96M Start-Up / Lock Time Time ⁽¹⁾	—	1.1	—	ms	VDD = VDDIO = 5.0V, f_IN = 32.768 kHz from XOSC32K, f_OUT = 96MHz
FDPLL_11	FDPLL_SRT	FDPLL96M Start-Up / Lock Time Time ⁽¹⁾	—	25	—	µs	VDD = VDDIO = 5.0V, f_IN = 2 MHz from XOSC, f_OUT = 96MHz

Note:

REFCLK for FDPLL96M is XOSC or XOSC32K.
DPLL jitter is sensitive to digital on-chip activity, which is application dependent.