46.2 Power Supply

Table 46-4. Power Supply Electrical Specifications
DC CHARACTERISTICS			Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
REG_1	VDDCORE_C_IN	VDDCORE Input Bypass parallel Capacitor pair	0.8	1	1.2	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω (Immediately adjacent to pin)
REG_3	VDDCORE_C_IN	VDDCORE Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to pin)
REG_4	VDDIO_C_IN	VDDIO Input Bypass parallel Capacitor pair	8	10⁽⁵⁾	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ⁽¹⁾
REG_5	VDDIO_C_IN	VDDIO Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to all VDDIO pins)
REG_7	VDDIN_C_IN	VDDIN Input Bypass parallel Capacitor pair	8	10⁽⁶⁾	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽¹⁾
REG_8	VDDIN_C_IN	VDDIN Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (immediately adjacent to all VDDIN pins)
REG_9	VREFA_C_IN	External VREFA Input Bypass parallel Capacitor pair (if used)	3.76	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_11	VREFA_C_IN		80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to pin)
REG_17	AVDD_C_IN	AVDD Input Bypass parallel Capacitor pair	8	10	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω⁽¹⁾ (as close as possible to pin)
REG_19	AVDD_C_IN	AVDD Input Bypass parallel Capacitor pair	80	100	—	nF	Ceramic XR7 with ESR <0.5Ω (Immediately adjacent to pin)
REG_23	AVDD_L_EXT	AVDD series Ferrite Bead DCR (DC Resistance)	—	—	0.1	Ω	≥600 Ohms @ 100MHz
REG_25	AVDD_L_EXT	Ferrite Bead current rating	500	—	—	mA	—
REG_36	VDDCORE	DC calibrated output voltage	1.08	1.23	1.32	V	—
REG_37	VDDIO, VDDIN, AVDD ⁽²⁾	VDDIO, VDDIN, AVDD Input Voltage Range	2.7	—	5.5	V	—
REG_43	SVDDIO/VDD_R	VDDIN, AVDD, VDDIO Rise Ramp Rate to Ensure Internal Power-on Reset Signal	—	—	0.1	V/µs	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_44	SVDDIO/VDD_F	VDDIN, AVDD, VDDIO Falling Ramp Rate to Ensure Internal Power-on Reset Signal	—	—	0.05	V/µs	Failure to meet this specification may cause the device to not detect reset
REG_45a	VPOR+	VDDIO/VDD Rising Power-on Reset	2.49	2.55	2.58	V	VDDIO/VDD Power up/Down (See Param REG_43, VDDIO/VDD Rise Ramp Rate)
REG_45b	VPOR-	VDDIO/VDD Falling Power-on Reset	1.64	1.75	1.92	V	VDDIO/VDD Power up/Down (See Param REG_44, VDDIO/VDD Fall Ramp Rate)
REG_47	VBODVDD ⁽³⁾	VDDBOD (All modes)	2.74	—	2.86	V	(Default setting) LEVEL[5:0] = 0x8 HYST[0] = 0x0
			2.74	—	2.94	V	(Default setting) LEVEL[5:0] = 0x8 ⁽⁴⁾ HYST[0] = 0x1
			5.27	—	5.48	V	LEVEL[5:0] = 0x3F HYST[0] = 0x0
			5.27	—	5.57	V	LEVEL[5:0] = 0x3F ⁽⁴⁾ HYST[0] = 0x1
REG_51	VBODVDD_{LEVEL_STEP}	VBODVDD step size, LEVEL[5:0]	—	46	—	mV	—
REG_52	VBODVDD_{HYST_STEP}⁽⁴⁾	VBODVDD Hysteresis	—	See Note (4)	—	mV	—
REG_53	T_RST	External RESET valid active pulse width	1.1	—	—	µs	Minimum reset active time to guarantee CPU reset

Note:

In single power supply configuration, only one bulk capacitor (REG_4 or REG_7) is enough for both VDDIN and VDDIO. In dual power supply configuration, two bulk capacitors are needed: REG_4 for VDDIO and REG_7 for VDDIN.
VDDIN and AVDD must be at the same voltage level. VDDIO should be lower or equal to VDDIN/ AVDD. The common voltage is referred to as VDD in the data sheet. Some I/O are in the VDDIO cluster, but can be multiplexed as analog inputs or outputs (e.g. PTC.X[n] pads). In such a case, AVDD is used to power the I/O. Using this configuration may result in an electrical conflict if the VDDIO voltage is lower than the VDDIN/AVDD.
VBODVDD(min) = 2.372 + d(BODVDD.LEVEL[5:0]) * 0.046.
(VBODVDD(max)@BODVDD.HYST[0]=1) = (VBODVDD(max)@BODVDD.HYST[0] = 0) + VBODVDDHYST_STEP.
Figure 46-1. VBODVDDHYST_STEP Graph
Shared between VDDIO, VDDIN and AVDD in case of a common power supply VDDIO=VDDIN=AVDD.
Shared between VDDIO, VDDIN and AVDD in case of a common power supply VDDIO=VDDIN=AVDD. Else, shared between VDDIN=AVDD.