38.7.36 Tx Buffer Element Size Configuration

This register is write-restricted and only writable if bit fields CCCR.CCE bit (CCCR <1>) = 1 and CCCR.INIT bit (CCCR <0>) = 1.

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes >8 bytes are intended for CAN FD operation only.

Table 38-53. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: TXESC
Offset: 0xC8
Reset: 0x00000000
Property: Write-restricted

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      TBDS[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 2:0 – TBDS[2:0] Tx Buffer Data Field Size

In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS (TXESC <2:0>), the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes).
ValueNameDescription
0x0DATA88 byte data field.
0x1DATA1212 byte data field.
0x2DATA1616 byte data field.
0x3DATA2020 byte data field.
0x4DATA2424 byte data field.
0x5DATA3232 byte data field.
0x6DATA4848 byte data field.
0x7DATA6464 byte data field.