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38.7.16 Interrupt Enable The settings in the
Interrupt Enable register determine which status changes in the Interrupt Register will
be signalled on an interrupt line.Table 38-33. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: IE Offset: 0x54 Reset: 0x00000000 Property: -
Bit 31 30 29 28 27 26 25 24 ARAE PEDE PEAE WDIE BOE EWE Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 EPE ELOE DRXE TOOE MRAFE TSWE Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 TEFLE TEFFE TEFWE TEFNE TFEE TCFE TCE HPME Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 RF1LE RF1FE RF1WE RF1NE RF0LE RF0FE RF0WE RF0NE Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 29 – ARAE Access to Reserved
Address Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 28 – PEDE Protocol Error in
Data Phase Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 27 – PEAE Protocol Error in
Arbitration Phase Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 26 – WDIE Watchdog Interrupt
Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 25 – BOE 'bus off' Status
Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 24 – EWE Error Warning
Status Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 23 – EPE Error Passive
Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 22 – ELOE Error Logging
Overflow Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 19 – DRXE Message stored to
Dedicated Rx Buffer Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 18 – TOOE Timeout Occurred
Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 17 – MRAFE Message RAM Access
Failure Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 16 – TSWE Timestamp
Wraparound Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 15 – TEFLE Tx Event FIFO Event
Lost Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 14 – TEFFE Tx Event FIFO Full
Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 13 – TEFWE Tx Event FIFO
Watermark Reached Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 12 – TEFNE Tx Event FIFO New
Entry Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 11 – TFEE Tx FIFO Empty
Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 10 – TCFE Transmission
Cancellation Finished Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 9 – TCE Transmission
Completed Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 8 – HPME High Priority
Message Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 7 – RF1LE Rx FIFO 1 Message
Lost Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 6 – RF1FE Rx FIFO 1 Full
Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 5 – RF1WE Rx FIFO 1 Watermark
Reached Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 4 – RF1NE Rx FIFO 1 New
Message Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 3 – RF0LE Rx FIFO 0 Message
Lost Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 2 – RF0FE Rx FIFO 0 Full
Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 1 – RF0WE Rx FIFO 0 Watermark
Reached Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
Bit 0 – RF0NE Rx FIFO 0 New
Message Interrupt Enable Value Description 0 Interrupt disabled. 1 Interrupt enabled.
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