38.7.4 Test
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TEST |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Write-restricted |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RX | TX[1:0] | LBCK | |||||||
| Access | R | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 7 – RX Receive Pin
| Value | Description |
|---|---|
| 0 | The CAN bus is dominant (CANx_RX = 0). |
| 1 | The CAN bus is recessive (CANx_RX = 1). |
Bits 6:5 – TX[1:0] Control of Transmit Pin
| Value | Name | Description |
|---|---|---|
| 0x0 | CORE | Reset value, CANx_TX controlled by CAN core, updated at the end of CAN bit time. |
| 0x1 | SAMPLE | Sample Point can be monitored at pin CANx_TX. |
| 0x2 | DOMINANT | Dominant (‘0’) level at pin CANx_TX. |
| 0x3 | RECESSIVE | Recessive (‘1’) level at pin CANx_TX. |
Bit 4 – LBCK Loop Back Mode
| Value | Description |
|---|---|
| 0 | Loop Back Mode is disabled. |
| 1 | Loop Back Mode is enabled. |