This register is
write-restricted and only writable if bit fields CCCR.CCE bit (CCCR <1>) = 1 and
CCCR.INIT bit (CCCR <0>) = 1.
Table 38-39. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
XIDAM
Offset:
0x90
Reset:
0x1FFFFFFF
Property:
Write-restricted
Bit
31
30
29
28
27
26
25
24
EIDM[28:24]
Access
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
Bit
23
22
21
20
19
18
17
16
EIDM[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
EIDM[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
EIDM[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bits 28:0 – EIDM[28:0] Extended ID
Mask
For acceptance
filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID
of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset
value of all bits set to one the mask is not active.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
