38.7.5 RAM Watchdog
This register is write-restricted and writable only if both CCCR.CCE bit
(CCCR <1>) and CCCR.INIT bit (CCCR <0>) are set.
The RAM Watchdog monitors the READY output of the Message RAM. A Message
RAM access via the CAN’s AHB Host Interface starts the Message RAM Watchdog Counter
with the value configured by WDC bits (RWD <7:0>). The counter is reloaded
with WDC bits (RWD <7:0>) when the Message RAM signals successful completion
by activating its READY output. In case there is no response from the Message RAM
until the counter has counted down to zero, the counter stops and interrupt IR.WDI
bit (IR<26>) is set.
Table 38-22. Register Bit Attribute
Legend| Symbol | Description | Symbol | Description | Symbol | Description |
|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RWD |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Write-restricted |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | WDV[7:0] | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | WDC[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – WDV[7:0] Watchdog
Value
Actual Message RAM
Watchdog Counter Value.
Bits 7:0 – WDC[7:0] Watchdog
Configuration
Start value of the
Message RAM Watchdog Counter. With the reset value of 0x00 the counter is
disabled.
