Note: Interrupt flags must be cleared and then read back to confirm the clear before
exiting the ISR to avoid double interrupts.
Table 38-64. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
ERROR
Offset:
0x100
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
BERR
Access
R/W
Reset
0
Bit 0 – BERR AHB Bus Error
Detection
The flag is set when
an AHB bus error is detected. The flag is cleared by writing a 1 to the
corresponding bit field. Writing a 0 has no effect. A hard reset will clear the
register. When the bit is set, the Error non-maskable interrupt is
generated.
Value
Description
0
No bus error detection.
1
Bus error detection.
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