38.7.45 Tx Event FIFO Status

Table 38-62. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: TXEFS
Offset: 0xF4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
       TEFLEFF 
Access RR 
Reset 00 
Bit 2322212019181716 
    EFPI[4:0] 
Access RRRRR 
Reset 00000 
Bit 15141312111098 
    EFGI[4:0] 
Access RRRRR 
Reset 00000 
Bit 76543210 
    EFFL[4:0] 
Access RRRRR 
Reset 00000 

Bit 25 – TEFL Tx Event FIFO Element Lost

This bit is a copy of interrupt flag IR.TEFL bit ( IR <15>). When IR.TEFL bit ( IR <15>) is reset, this bit is also reset.

ValueDescription
0No Tx Event FIFO element lost.
1Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.

Bit 24 – EFF Event FIFO Full

ValueDescription
0Tx Event FIFO not full.
1Tx Event FIFO full.

Bits 20:16 – EFPI[4:0] Event FIFO Put Index

Tx Event FIFO write index pointer, range 0 to 31.

Bits 12:8 – EFGI[4:0] Event FIFO Get Index

Tx Event FIFO read index pointer, range 0 to 31.

Bits 4:0 – EFFL[4:0] Event FIFO Fill Level

Number of elements stored in Tx Event FIFO, range 0 to 32.