38.7.31 Rx FIFO 1 Status

Table 38-48. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: RXF1S
Offset: 0xB4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 DMS[1:0]    RF1LF1F 
Access RRRR 
Reset 0000 
Bit 2322212019181716 
   F1PI[5:0] 
Access RRRRRR 
Reset 000000 
Bit 15141312111098 
   F1GI[5:0] 
Access RRRRRR 
Reset 000000 
Bit 76543210 
  F1FL[6:0] 
Access RRRRRRR 
Reset 0000000 

Bits 31:30 – DMS[1:0] Debug Message Status

This field defines the debug message status.

ValueNameDescription
0x0IDLEIdle state, wait for reception of debug messages, DMA request is cleared.
0x1DBGADebug message A received.
0x2DBGBDebug message A, B received.
0x3DBGCDebug message A, B, C received, DMA request is set.

Bit 25 – RF1L Rx FIFO 1 Message Lost

This bit is a copy of interrupt flag IR.RF1L bit (IR <7>). When IR.RF1L bit (IR <7>) is reset, this bit is also reset.

Overwriting the oldest message when RXF1C.F1OM bit (RXF1C <31>) = ‘1’ will not set this flag.

ValueDescription
0No Rx FIFO 1 message lost.
1Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.

Bit 24 – F1F Rx FIFO 1 Full

ValueDescription
0Rx FIFO 1 not full.
1Rx FIFO 1 full.

Bits 21:16 – F1PI[5:0] Rx FIFO 1 Put Index

Rx FIFO 1 write index pointer, range 0 to 63.

Bits 13:8 – F1GI[5:0] Rx FIFO 1 Get Index

Rx FIFO 1 read index pointer, range 0 to 63.

Bits 6:0 – F1FL[6:0] Rx FIFO 1 Fill Level

Number of elements stored in Rx FIFO 1, range 0 to 64.