38.7.10 Timeout Counter Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TOCC |
| Offset: | 0x28 |
| Reset: | 0xFFFF0000 |
| Property: | Write-restricted |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TOP[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TOP[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TOS[1:0] | ETOC | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 31:16 – TOP[15:0] Timeout Period
Bits 2:1 – TOS[1:0] Timeout Select
| Value | Name | Description |
|---|---|---|
| 0x0 | CONT | Continuous operation. |
| 0x1 | TXEF | Timeout controlled by TX Event FIFO. |
| 0x2 | RXF0 | Timeout controlled by Rx FIFO 0. |
| 0x3 | RXF1 | Timeout controlled by Rx FIFO 1. |
Bit 0 – ETOC Enable Timeout Counter
| Value | Description |
|---|---|
| 0 | Timeout Counter disabled. |
| 1 | Timeout Counter enabled. |