38.7.43 Tx Buffer Cancellation Finished Interrupt Enable

Table 38-60. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: TXBCIE
Offset: 0xE4
Reset: 0x00000000
Property: -

Bit 3130292827262524 
 CFIE31CFIE30CFIE29CFIE28CFIE27CFIE26CFIE25CFIE24 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 CFIE23CFIE22CFIE21CFIE20CFIE19CFIE18CFIE17CFIE16 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 CFIE15CFIE14CFIE13CFIE12CFIE11CFIE10CFIE9CFIE8 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CFIE7CFIE6CFIE5CFIE4CFIE3CFIE2CFIE1CFIE0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – CFIEn Cancellation Finished Interrupt Enable

Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
ValueDescription
0Cancellation finished interrupt disabled.
1Cancellation finished interrupt enabled.