38.7.40 Tx Buffer Transmission Occurred

Table 38-57. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: TXBTO
Offset: 0xD8
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 TO31TO30TO29TO28TO27TO26TO25TO24 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 TO23TO22TO21TO20TO19TO18TO17TO16 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 TO15TO14TO13TO12TO11TO10TO9TO8 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 TO7TO6TO5TO4TO3TO2TO1TO0 
Access RRRRRRRR 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – TOn Transmission Occurred

Each Tx Buffer has its own Transmission Occurred bit.

The bits are set when the corresponding TXBRP bit is cleared after a successful transmission.

The bits are reset when a new transmission is requested by writing ‘1’ to the corresponding bit of register TXBAR.