38.7.17 Interrupt Line Select
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ILS |
| Offset: | 0x58 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ARAL | PEDL | PEAL | WDIL | BOL | EWL | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EPL | ELOL | DRXL | TOOL | MRAFL | TSWL | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TEFLL | TEFFL | TEFWL | TEFNL | TFEL | TCFL | TCL | HPML | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RF1LL | RF1FL | RF1WL | RF1NL | RF0LL | RF0FL | RF0WL | RF0NL | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 29 – ARAL Access to Reserved Address Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 28 – PEDL Protocol Error in Data Phase Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 27 – PEAL Protocol Error in Arbitration Phase Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 26 – WDIL Watchdog Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 25 – BOL 'bus off' Status Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 24 – EWL Error Warning Status Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 23 – EPL Error Passive Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 22 – ELOL Error Logging Overflow Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 19 – DRXL Message stored to Dedicated Rx Buffer Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 18 – TOOL Timeout Occurred Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 17 – MRAFL Message RAM Access Failure Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 16 – TSWL Timestamp Wraparound Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 15 – TEFLL Tx Event FIFO Event Lost Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 14 – TEFFL Tx Event FIFO Full Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 13 – TEFWL Tx Event FIFO Watermark Reached Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 12 – TEFNL Tx Event FIFO New Entry Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 11 – TFEL Tx FIFO Empty Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 10 – TCFL Transmission Cancellation Finished Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 9 – TCL Transmission Completed Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 8 – HPML High Priority Message Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 7 – RF1LL Rx FIFO 1 Message Lost Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 6 – RF1FL Rx FIFO 1 Full Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 5 – RF1WL Rx FIFO 1 Watermark Reached Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 4 – RF1NL Rx FIFO 1 New Message Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 3 – RF0LL Rx FIFO 0 Message Lost Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 2 – RF0FL Rx FIFO 0 Full Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 1 – RF0WL Rx FIFO 0 Watermark Reached Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |
Bit 0 – RF0NL Rx FIFO 0 New Message Interrupt Line
| Value | Description |
|---|---|
| 0 | Interrupt assigned to CAN interrupt line 0. |
| 1 | Interrupt assigned to CAN interrupt line 1. |