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38.7.1 Endian
Table 38-18. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: ENDN Offset: 0x04 Reset: 0x87654321 Property: Read-only
Bit 31 30 29 28 27 26 25 24 ETV[31:24] Access R R R R R R R R Reset 1 0 0 0 0 1 1 1
Bit 23 22 21 20 19 18 17 16 ETV[23:16] Access R R R R R R R R Reset 0 1 1 0 0 1 0 1
Bit 15 14 13 12 11 10 9 8 ETV[15:8] Access R R R R R R R R Reset 0 1 0 0 0 0 1 1
Bit 7 6 5 4 3 2 1 0 ETV[7:0] Access R R R R R R R R Reset 0 0 1 0 0 0 0 1
Bits 31:0 – ETV[31:0] Endianness Test
Value The endianness test
value is 0x87654321
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