38.7.27 Rx FIFO 0 Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RXF0S |
| Offset: | 0xA4 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RF0L | F0F | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| F0PI[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| F0GI[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| F0FL[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 25 – RF0L Rx FIFO 0 Message Lost
This bit is a copy of interrupt flag IR.RF0L bit (IR <3>). When IR.RF0L bit (IR <3>) is reset, this bit is also reset.
Overwriting the oldest message when RXF0C.F0OM bit (RXF0C <31>) = ‘1’ will not set this flag.
| Value | Description |
|---|---|
| 0 | No Rx FIFO 0 message lost. |
| 1 | Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. |
Bit 24 – F0F Rx FIFO 0 Full
| Value | Description |
|---|---|
| 0 | Rx FIFO 0 not full. |
| 1 | Rx FIFO 0 full. |