38.7.27 Rx FIFO 0 Status

Table 38-44. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: RXF0S
Offset: 0xA4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
       RF0LF0F 
Access RR 
Reset 00 
Bit 2322212019181716 
   F0PI[5:0] 
Access RRRRRR 
Reset 000000 
Bit 15141312111098 
   F0GI[5:0] 
Access RRRRRR 
Reset 000000 
Bit 76543210 
  F0FL[6:0] 
Access RRRRRRR 
Reset 0000000 

Bit 25 – RF0L Rx FIFO 0 Message Lost

This bit is a copy of interrupt flag IR.RF0L bit (IR <3>). When IR.RF0L bit (IR <3>) is reset, this bit is also reset.

Overwriting the oldest message when RXF0C.F0OM bit (RXF0C <31>) = ‘1’ will not set this flag.

ValueDescription
0No Rx FIFO 0 message lost.
1Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero.

Bit 24 – F0F Rx FIFO 0 Full

ValueDescription
0Rx FIFO 0 not full.
1Rx FIFO 0 full.

Bits 21:16 – F0PI[5:0] Rx FIFO 0 Put Index

Rx FIFO 0 write index pointer, range 0 to 63.

Bits 13:8 – F0GI[5:0] Rx FIFO 0 Get Index

Rx FIFO 0 read index pointer, range 0 to 63.

Bits 6:0 – F0FL[6:0] Rx FIFO 0 Fill Level

Number of elements stored in Rx FIFO 0, range 0 to 64.