38.7.14 Transmitter Delay Compensation

Table 38-31. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: TDCR
Offset: 0x48
Reset: 0x00000000
Property: Write-restricted

This register is write-restricted and only writable if bit fields CCCR.CCE bit (CCCR <1>) = 1 and CCCR.INIT bit (CCCR <0>) = 1.

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  TDCO[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
  TDCF[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 14:8 – TDCO[6:0] Transmitter Delay Compensation Offset

ValueDescription
0x00 - 0x7FOffset value defining the distance between the measured delay from CANx_TX to CANx_RX and the secondary sample point. Valid values are 0 to 127 mtq.

Bits 6:0 – TDCF[6:0] Transmitter Delay Compensation Filter Window Length

ValueDescription
0x00 - 0x7FDefines the minimum value for the SSP position, dominant edges on CANx_RX that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq.