38.7.13 Protocol Status

Note:
  1. When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in PSR.DLEC bit field (PSR<10:8>) instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error.
  2. The 'bus off' recovery sequence (see CAN Specification Rev. 2.0 or ISO 11898-1) cannot be shortened by setting or resetting CCCR.INIT bit (CCCR <0>). If the device goes 'bus off', it will set CCCR.INIT bit (CCCR <0>) of its own accord, stopping all bus activities. Once CCCR.INIT bit (CCCR <0>) has been cleared by the CPU, the device will wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the'bus off' recovery sequence, the Error Management Counters will be reset. During the wait time after the resetting of CCCR.INIT bit (CCCR <0>), each time a sequence of 11 recessive bits is monitored, a Bit0 Error code is written to PSR.LEC bit field (PSR <2:0>). This enables the CPU to readily check the status of CAN bus (whether bus is stuck at dominant level or continuously disturbed). ECR.REC bit-field (ECR<14:8>) is used to count these sequences.
Table 38-30. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: PSR
Offset: 0x44
Reset: 0x00000707
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  TDCV[6:0] 
Access RRRRRRR 
Reset 0000000 
Bit 15141312111098 
  PXERFDFRBRSRESIDLEC[2:0] 
Access RRRRRRR 
Reset 0000111 
Bit 76543210 
 BOEWEPACT[1:0]LEC[2:0] 
Access RRRRRRRR 
Reset 00000111 

Bits 22:16 – TDCV[6:0] Transmitter Delay Compensation Value

ValueDescription
0x00 - 0x7FPosition of the secondary sample point, defined by the sum of the measured delay from CANx_TX to CANx_RX and TDCR.TDCO bit-field (TDCR <14:8>). The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.

Bit 14 – PXE Protocol Exception Event

This field is cleared on read access. A recessive “reserved bit” following a recessive FDF bit is the example of Protocol Exception.
ValueDescription
0No protocol exception event occurred since last read access.
1Protocol exception event occurred.

Bit 13 – RFDF Received a CAN FD Message

This field is cleared on read access.
ValueDescription
0Since this bit was reset by the CPU, no CAN FD message has been received.
1Message in CAN FD format with FDF flag set has been received. This bit is set independent of acceptance filtering.

Bit 12 – RBRS BRS flag of last received CAN FD Message

This field is cleared on read access.
ValueDescription
0Last received CAN FD message did not have its BRS flag set.
1Last received CAN FD message had its BRS flag set. This bit is set together with RFDF, independent of acceptance filtering.

Bit 11 – RESI ESI flag of last received CAN FD Message

This field is cleared on read access.
ValueDescription
0Last received CAN FD message did not have its ESI flag set.
1Last received CAN FD message had its ESI flag set.

Bits 10:8 – DLEC[2:0] Data Last Error Code

Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.

Bit 7 – BO 'bus off' Status

ValueDescription
0The CAN is not 'bus off' state.
1The CAN is in 'bus off' state.

Bit 6 – EW Error Warning Status

ValueDescription
0Both error counters are below the Error Warning limit of 96.
1At least one of the error counter has reached the Error Warning limit of 96.

Bit 5 – EP Error Passive

ValueDescription
0The CAN is in the ‘error active’ state. It normally takes part in bus communication and sends an active error flag when an error has been detected.
1The CAN is in the 'error passive' state.

Bits 4:3 – ACT[1:0] Activity

Monitors the module’s CAN communication state.
ValueNameDescription
0x0SYNCNode is synchronizing on CAN communication.
0x1IDLENode is neither receiver nor transmitter.
0x2RXNode is operating as receiver.
0x3TXNode is operating as transmitter.

Bits 2:0 – LEC[2:0] Last Error Code

The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmission) without error.

This field is set on read access.

ValueNameDescription
0x0NONENo Error: No error occurred since LEC has been reset by successful reception or transmission.
0x1STUFFStuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x2FORMForm Error: A fixed format part of a received frame has the wrong format.
0x3ACKAck Error: The message transmitted by the CAN was not acknowledged by another node.
0x4BIT1Bit1 Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus was dominant.
0x5BIT0Bit0 Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive. During 'bus off' recovery this status is set each time a sequence of 11 recessive bits have been monitored. This enables the CPU to monitor the proceeding of the 'bus off' recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x6CRCCRC Error: The CRC checksum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
0x7NCNo Change: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register.