21.3.71 publish_block

Description

Tcl command publishes a block with the conditions related to place and route. This is the project_setting command. To enable Block Creation for a new project:

Select New Project from the Libero SoC Project menu.
Check the Enable Block Creation checkbox.
Select the Enhanced Constraint Flow for the new project. In an existing project, from the Project menu, select Project Settings > Design Flow and check the Enable Block Creation checkbox.
After Block Creation is enabled, Publish Block appears in the Design Flow window.
Expand Publish Design, right-click Publish Block and select Export from the context-menu that appears. By default, this option is not unchecked.

publish_block -file {absolute or relative path} \
              [-publish_placement value] \
              [-publish_routing value] \
              [-publish_region value] \
              [-vhdl value ]

Arguments


Parameter	Type	Description
file	string	Specifies the location (absolute or relative) to publish the block. Default is /designer/<designer_name>/<designer_name>.cxz.
publish_placement	boolean	Valid values are: TRUE, 1, true, FALSE, 0 or false FALSE, false, 0 - no placement or routing will be published and preserved. Only the netlist is preserved. TRUE, true, 1 - publishes placement if all the macros in your design are placed or assigned to a region. Default this box is checked.
publish_routing	boolean	Valid values are: TRUE, 1, true, FALSE, 0 or false FALSE, false, 0 - routing will not be published and added to the block. This block will be completely rerouted completely in the top design. TRUE, true, 1 - publish routing to be part of the block. `publish_placement` must be 1 for this option to take effect. All the macros should be placed or assigned to a region. Default this box is checked.
publish_region	boolean	Valid values are: TRUE, 1, true, FALSE, 0 or false FALSE, false, 0 - region constraints are not added to the block published. TRUE, true, 1 - Region constraints will be published and preserved. This is not recommended and should be done only if the user wants to keep the regions in the top design. Example: the user wants to see an empty region in the top design. In general, the regions used to control placement should not be part of the block. Default this box is checked.
vhdl	boolean	Valid values are: TRUE, 1, true, FALSE, 0 or false FALSE, false, 0 - generates a Verilog netlist to be used for synthesis and simulation. Default value. TRUE, true, 1 - generates a VHDL file format.

Error Codes


Error Code	Description
None	Required parameter 'file' is missing.
None	Required parameter 'publish_placement' is missing.
None	Required parameter 'publish_routing' is missing.
None	Required parameter 'publish_region' is missing.
None	publish_placement: Invalid argument value: 'value' (expecting TRUE, 1, true, FALSE, 0 or false).
None	publish_routing: Invalid argument value: '' (expecting TRUE, 1, true, FALSE, 0 or false).
None	publish_region: Invalid argument value: 'value' (expecting TRUE, 1, true, FALSE, 0 or false).
None	vhdl: Invalid argument value: 'value' (expecting TRUE, 1, true, FALSE, 0 or false).
None	Parameter 'param_name' is not defined. Valid command formatting is 'publish_block -file "Publish Block file Name" \ -publish_placement "TRUE \| FALSE" \ -publish_routing "TRUE \| FALSE" \ -publish_region "TRUE \| FALSE" \ [-vhdl "TRUE \| FALSE"]'.

Supported Families


Supported Families
PolarFire®
RTG4™
SmartFusion® 2
IGLOO® 2

Example

The following example exports Publish Block file in the \test_block\designer\top\top.cxz file, generates a Verilog netlist. Publishes placement and region if all the macros in your design are placed or assigned to a region:

publish_block -file {D:\test_block\designer\top\top.cxz} \
              -publish_placement 1 -publish_routing 1 -publish_region 1 \
              -vhdl 0

v2024.2