21.3.89 set_modelsim_options

Description

This Tcl command sets your ModelSim simulation options. You can set change how Libero SoC handles Do files in simulation, import your own Do files, set simulation run time, and change the DUT name used in your simulation. You can sets options from the Project Settings > Simulation menu. Default values are used if parameters are omitted.

set_modelsim_options \
[-use_automatic_do_file "TRUE | FALSE"] \
[-user_do_file {path}] \
[-sim_runtime {value}] \
[-tb_module_name {value}] \
[-tb_top_level_name {value}] \
[-include_do_file "TRUE | FALSE" \
[-included_do_file {value}] \
[-type {value}] \
[-resolution {value}] \
[-add_vsim_options {value}] \
[-display_dut_wave "TRUE | FALSE"] \
[-log_all_signals "TRUE | FALSE"] \
[-do_file_args {value}] \
[-dump_vcd "TRUE | FALSE"] \
[-vcd_file "VCD file name"] \
[-sdf_corner "sdf_corner"] \
[-verilog {value}] \
[-VHDL {value}] \
[-disable_pulse_filtering "TRUE | FALSE"] \
[-timeunit {value}] \
[-timeunit_base {value}] \
[-precision {value}] \
[-precision_base {value}]

Arguments

ParameterTypeDescription
use_automatic_do_filebooleanAutomatically create a DO file that enables you to simulate your design. Following are the valid values:
  • TRUE, true, 1 - uses the default automatic.do file in your project. This box is checked by default.
  • FALSE, false, 0 - uses a different *.do file; use the other simulation options to specify it.
user_do_filestringSpecifies the location of your user-defined *.do file.
sim_runtimenumber and unit of timeSets your simulation runtime. It is optional. Value is the number and unit of time, such as {1000 ns}.
tb_module_namestringSpecifies your test bench module name, where value is the name. Default value is "test bench".
tb_top_level_namestringSets the top-level instance name in the test bench, where value is the name. Default is <top>_0.
include_do_filebooleanEnables you to include DO file. Valid values are:
  • TRUE, true, 1 - Includes the *.do file.
  • FALSE, false, 0 - Does not include the *.do file.
included_do_filestringSpecifies the path of the included *.do file, where the value is the name of the file. Including a DO file enables you to customize the set of signal waveforms that will be displayed in ModelSim. Specify this argument with -include_do_file argument. Default is work.do.
typestringResolution type; possible values are:
  • min - minimum. This is the default value.
  • typ - typical.
  • max - maximum.
resolutionunit of timeSets your resolution value. Value is the number and unit of time, such as {1ps}. The default is family-specific, but you can customize it to fit your needs.
add_vsim_optionsstringAdds more Vsim options, where value specifies the option(s).
display_dut_wavebooleanEnables ModelSim to display signals for the tested design. Following are the possible values:
  • FALSE, false, 0 - displays the signal for the top_level_test bench.
  • TRUE, true, 1 - enables ModelSim to display the signals for the tested design.
log_all_signalsbooleanSaves and logs all signals during simulation.
  • TRUE, true, 1 - logs all signals.
  • FALSE, false, 0 - does not log all signals. Default this box checked.
do_file_argslist of stringsSpecifies *.do file command parameters. Default is empty.
dump_vcdbooleanDumps the VCD file when simulation is complete. Following are the possible values:
  • TRUE, true, 1 - dumps the VCD file
  • FALSE, false, 0 - does not dump the VCD file. Default this box checked.
vcd_filestringSpecifies the name of the dumped VCD file, where value is the name of the file. Default is "power.vcd".
sdf_corner {parameter}stringSets the corner on which the post layout simulation will be done.
  • slow_lv_ht - slow process, low voltage and high temperature operating conditions. Default value.
  • slow_lv_lt - slow process, low voltage and low temperature operating conditions.
  • fast_hv_lt - fast process, high voltage and low temperature operating conditions.
verilogintegerHDL Testbench file type can be either Verilog or VHDL, possible values are: 1 or 0. Default value is 0.
VHDLintegerHDL Testbench file type can be either Verilog or VHDL, possible values are: 1 or 0. Default value is 0.
disable_pulse_filteringbooleanSpecifies to enable/disable pulse filtering during SDF based simulations.
  • TRUE, true, 1 - enable pulse filtering.
  • FALSE, false, 0 - disable pulse filtering. The default value is false.
timeunitintegerTimeScale time unit value. Default value is 1.
timeunit_baseunit of timeTimeScale precision base value. The default setting is ns, possible values are:
  • s - second
  • ms - milisecond
  • us - microsecond
  • ns - nanosecond
  • ps - picosecond
  • fs - femtosecond
precisionintegerTimeScale precision value. Default value is 100.
precision_baseunit of timeTimeScale precision base value. The default setting is ps; possible values are:
  • s - second
  • ms - milisecond
  • us - microsecond
  • ns - nanosecond
  • ps - picosecond
  • fs - femtosecond

Supported Families

Supported Families
PolarFire®
RTG4™
SmartFusion® 2
IGLOO® 2

Example

Sets ModelSim options to use the automatic *.do file, sets simulation runtime to 1000 ns, sets the testbench module name to "testbench", sets the testbench top level to top_0, sets simulation type to "max", resolution to 1 ps, adds no vsim options, does not log signals, adds no additional DO file arguments, dumps the VCD file with a name power.vcd.

set_modelsim_options -use_automatic_do_file 1 -sim_runtime {1000ns} \
-tb_module_name {testbench} -tb_top_level_name {top_0} -include_do_file 0 \
-type {max} -resolution {1ps} -add_vsim_options {} -display_dut_wave 0 \
-log_all_signals 0 -do_file_args {} - dump_vcd 0 -vcd_file {power.vcd}

See Also