21.3.70 project_settings

Description

This Tcl command modifies project flow settings for your Libero SoC project. The Project Settings dialog box enables you to modify your Device, HDL, and Design Flow settings and your Simulation Options. In Libero SoC, from the Project menu, click Project Settings.

project_settings \
[-hdl "VHDL | VERILOG"] \
[-verilog_mode "SYSTEM_VERILOG | VERILOG_2K"] \
[-vhdl_mode "VHDL_2008 | VHDL_93"] \
[-auto_update_modelsim_ini "TRUE | FALSE"] \
[-auto_update_viewdraw_ini "TRUE | FALSE"] \
[-standalone_peripheral_initialization "TRUE | FALSE"] \
[-ondemand_build_dh "TRUE | FALSE"] \
[-auto_generate_synth_hdl "TRUE | FALSE"] \
[-auto_run_drc "TRUE | FALSE"] \
[-auto_generate_viewdraw_hdl "TRUE | FALSE"] \
[-auto_file_detection "TRUE | FALSE"] \
[-enable_set_mitigation "TRUE | FALSE"] \
[-enable_design_separation "TRUE" | "FALSE"] \
[-display_fanout_limit "display_fanout_limit"] \
[-block_mode "TRUE | FALSE"] \
[-abort_flow_on_sdc_errors "TRUE | FALSE"] \
[-abort_flow_on_pdc_errors "TRUE | FALSE"] \
[-sim_flow_mode "TRUE | FALSE"] \
[-auto_generate_physynth_hdl "TRUE | FALSE"] \
[-instantiate_in_smartdesign "TRUE | FALSE"] \
[-enable_viewdraw "TRUE | FALSE"] \
[-vm_netlist_flow "TRUE | FALSE"]
[-system_verilog_mfcu "TRUE | FALSE"]

Arguments

ParameterTypeDescription
hdlstringSets your project HDL type. Valid values are: VHDL or VERILOG.
verilog_modestringSets the Verilog standard to Verilog-2001 or System Verilog. Valid values are: VERILOG_2K or SYSTEM_VERILOG. The default value is SYSTEM_VERILOG.
vhdl_modestringSets the VHDL standard. Valid values are: VHDL-2008 or VHDL-1993. The default value is VHDL-2008.
auto_update_modelsim_inibooleanSets your auto-update modelsim.ini file option. Valid values are True, true, 1, FALSE, false or 0:
  • TRUE, true, 1 - updates the modelsim.ini file automatically. The default value is 1.
  • FALSE, false, 0 - modelsim.ini file does not update automatically.
auto_update_viewdraw_inibooleanSets your auto-update viewdraw.ini file option. Valid values are True, true, 1, FALSE, false or 0:
  • TRUE, true, 1 - updates the viewdraw.ini file automatically. The default value is 1.
  • FALSE, false, 0 - viewdraw.ini file does not update automatically.
block_modebooleanEnables you to create and publish design blocks (*.cxz files) in Libero SoC. Puts the Project Manager in Block mode, Design blocks are low-level components that may have completed the place-and-route step and met the timing and power requirements. These low-level design blocks can then be imported into a Libero SoC project and re-used as components in a higher level design. By default, this box is unchecked.
  • TRUE, true, 1 - Enable to create and publish design blocks file.
  • FALSE, false, 0 - Disables to create and publish design blocks file.
auto_generate_synth_hdlbooleanAuto-generates your HDL file after synthesis. Valid values are:
  • TRUE, true, 1 - enables auto-generation of your HDL file after synthesis.
  • FALSE, false, 0 - disables auto-generation of your HDL file after synthesis. The default value is 0.
auto_run_drcbooleanAutomatically runs the design rule check immediately after synthesis. Valid values are:
  • TRUE, true, 1 - enables auto-runs the design rule check immediately after synthesis.
  • FALSE, false, 0 - disables auto-runs the design rule check immediately after synthesis. the default value is 0.
auto_generate_viewdraw_hdlbooleanAutomatically generates your HDL netlist after Save and Check in ViewDraw. Valid values are:
  • TRUE, true, 1 - enables auto-generates your HDL netlist. The default value is 1.
  • FALSE, false, 0 - disables auto-generates your HDL netlist.
auto_file_detectionbooleanAutomatically detects when new files have been added to the Libero SoC project folder. Valid values are:
  • TRUE, true, 1 - automatically detects new added files in Libero SoC project. The default value is 1.
  • FALSE, false, 0 - automatically does not detects new added files in Libero SoC project.
standalone_peripheral_initializationbooleanUse Standalone Initialization for MDDR/FDDR/SERDES Peripherals – Check this box if you want to create your own peripheral initialization logic in SmartDesign for each of your design peripherals (MDDR/FDDR/SERDES). When checked, System Builder does not build the peripherals initialization logic for you. Standalone initialization is useful if you want to make the initialization logic of each peripheral separate from and independent of each other. By default, this box is checked. Valid values are: TRUE, true, 1 , FALSE, false or 0.
ondemand_build_dhintegerEnable/disable On Demand Build Design Hierarchy. Valid values are: TRUE, true, 1, FALSE, false or 0. The default value is 1.
enable_set_mitigationbooleanEnable Single Event Transient mitigation - Controls the mitigation of Single Event Transient (SET) in the FPGA fabric. When this box is checked, SET filters are turned on globally (including URAM, LSRAM, MACC, I/O FF, Regular FF, DDR_IN, DDR_OUT) to help mitigate radiation-induced transients. By default, this box is unchecked. Valid values are: TRUE, true, 1, FALSE, false or 0.
enable_design_separationintegerSet it to “1” if your design is for security and safety critical applications and you want to make your design’s individual subsystems (design blocks) separate and independent (in terms of physical layout and programming) to meet your design separation requirements. When set to “1”, Libero generates a parameter file (MSVT.param) that details design blocks present in the design and the number of signals entering and leaving a design block. Microchip provides a separate tool, known as Microchip Separation Verification Tool (MSVT), which checks the final design place and route result against the MSVT.param file and determines whether the design separation meets your requirements. The default value is 1. This option available for SmartFusion 2 and IGLOO 2.
display_fanout_limitintegerUse this option to set the limit of high fanout nets to be displayed; the default value is 10. This means the top 10 nets with the highest fanout will appear in the root_compile_netlist.log file.
abort_flow_on_pdc_errorsbooleanAbort flow if errors are found in Physical Design Constraints(PDC). Valid values are: TRUE, true, 1, FALSE, false or 0. By default, this box is checked.
abort_flow_on_sdc_errorsbooleanAbort flow if errors are found in Timing Constraints (SDC). Valid values are: TRUE, true, 1, FALSE, false or 0. By default, this box is checked.
auto_generate_physynth_hdlbooleanAuto-generates your HDL file after physical synthesis. Valid values are: TRUE, true, FALSE, false or 0. The default value is 1.
instantiate_in_smartdesignbooleanInstantiate System Builder/MSS component in a SmartDesign on creation - Uncheck this box if you are using this project to create System Builder or MSS components and do not plan on using them in a SmartDesign based design. This is especially useful for design flows where the System Builder or MSS components are stitched in a design using HDL. Valid values are: TRUE, true, 1, FALSE, false or 0.
enable_viewdrawbooleanEnable/disable to create a schematic source file in Libero SoC. Valid values are: TRUE, true, 1, FALSE, false or 0.
vm_netlist_flowbooleanSets Synthesis gate level netlist format. By default, this box is checked. Valid values are: TRUE, true, 1, FALSE, false or 0.
  • TRUE, true, 1 - sets Verilog netlist format.
  • FALSE, false, 0 - sets EDIF netlist format.
sim_flow_modebooleanInstantiate simulation cores in your SmartDesign Testbench. Simulation cores are basic cores that are useful for stimulus, such as driving clocks, resets, and pulses. Valid values are: TRUE, true, 1, FALSE, false or 0.
system_verilog_mfcubooleanEnable/disable the System Verilog Multi-File Compilation Unit (MFCU). Valid values are: TRUE, true, 1, FALSE, false or 0.
Note: This option is only applicable when -verilog_mode is “SYSTEM_VERILOG”.

Supported Families

Supported Families
PolarFire®
RTG4™
SmartFusion® 2
IGLOO® 2

Example

Example of SmartFusion 2, IGLOO 2:

The following example sets your project to VHDL, disables the auto-update of the ModelSim INI or ViewDraw INI files, enables the automatically generation of HDL after synthesis, enables auto-detection for files, sets the display of high fanout nets to the top 12 high fanout nets, enables SET filters to mitigate radiation-induced transients, and enables design separation methodology for the design.

project_settings -hdl "VHDL" \
-auto_update_modelsim_ini "FALSE" \
-auto_update_viewdraw_ini "FALSE"\
-block_mode "FALSE" -auto_generate_synth_hdl "TRUE" \
-auto_file_detection "TRUE" \
-display_fanout_limit {12} \
-enable_set_mitigation {1}