18.3.3 RDC Status Register
- The transition of SYNCCNTSTAT may trail the assertion of the RDC sync pulse by 2-3 UPB clock cycles due to synchronization between clock domains.
- The POLFBVAL bit is valid
only if ON(RDCCON[15]) =
1and EXCSYNCEN(RDCEXCCON[15]) =1.
Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit
can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as
'0'; -n = Value at POR; '1' = bit is set;
'0' = bit is cleared; x = bit value is unknown
| Name: | RDCSTAT |
| Offset: | 0x001F98 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SYNCCNTSTAT[7:0] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CORDICDONE | POLFBVAL | IMUXCFGERR | CICINOVF | ||||||
| Access | R/HS/HC | R/HS/HC | R/W/HS | R/W/HS | |||||
| Reset | 1 | 0 | 0 | 0 |
Bits 15:8 – SYNCCNTSTAT[7:0] Excitation Signal Synchronization Counter Status bits(1)
| Value | Description |
|---|---|
| xx | After beginning an excitation signal software synchronization operation by setting the value of SYNCCNT(RDCEXCCON[23:16]) and setting EXCSYNCEN(RDCEXCCON[15]), reads of this bitfield will return the remaining count of cycles until the ADC triggers and excitation signals are generated. If the EXCSYNCEN bit is cleared during the sync period, the value in SYNCCNTSTAT will be kept at the last value that was decremented by the counter. |
Bit 7 – CORDICDONE CORDIC Algorithm Done bit
| Value | Description |
|---|---|
1 |
The CORDIC block input processing is complete, and the RDCCORDXOUT and RDCCORDYOUT registers have been updated with the x and y values. |
0 |
The CORDIC algorithm processing has not yet been completed. |
Bit 6 – POLFBVAL RDC Feedback Polarity Value bit(2)
| Value | Description |
|---|---|
x |
The value of the CIC filter polarity feedback signal for diagnostics. This is equivalent to the polarity of the external signal fed to the CIC filter. |
0 |
Read as 0 if the conditions for operation are not met as per Note 2. |
Bit 1 – IMUXCFGERR RDC Configuration Error bit
| Value | Description |
|---|---|
1 |
An unimplemented ADC module instance value has been written to IMUX0 (RDCINSEL[2:0]) or IMUX1 (RDCINSEL[18:16]). |
0 |
The values of the IMUX0 (RDCINSEL[2:0]) and IMUX1 (RDCINSEL[18:16]) bits are valid. |
Bit 0 – CICINOVF CIC Filter Input Overflow Error bit
| Value | Description |
|---|---|
1 |
An input sample valid signal was asserted before a previous CIC filter input was processed. |
0 |
No error condition has occurred. |