18.3.4 RDC Excitation Signal Control Register

Note:
  1. Writes to these bits while EXCSYNCEN(RDCEXCCON[15]) = 1 will be ignored.
  2. Writes to these bits when ON(RDCCON[15]) = 1 will be ignored.

Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as '0'; -n = Value at POR; '1' = bit is set; '0' = bit is cleared; x = bit value is unknown

Name: RDCEXCCON
Offset: 0x001F9C

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 SYNCCNT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 EXCSYNCENEXCOE       
Access R/WR/W 
Reset 00 
Bit 76543210 
     EXCFDIV[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 23:16 – SYNCCNT[7:0]  Excitation Signal Firmware Synchronization Counter bits(1)

The module will gate off excitation and ADC trigger output signals for the specified number of RDC input clock cycles minus 1 after the EXCSYNCEN bit is set.

Bit 15 – EXCSYNCEN Excitation Signal Firmware Synchronization bit

ValueDescription
1

Copy the value of the SYNCCNT bitfield into the SYNCCNTSTAT bitfield and begin decrementing the SYNCCNTSTAT counter. After a number of RDC input clocks specified by SYNCCNT, along with an additional 2-3 clocks for synchronization, the synchronization signal will be asserted for one RDC input clock period. This will be followed by the generation of RDC excitation output and triggering of the ADC. If this bit is set when SYNCCNT equals zero, it will have the same effect as setting it when SYNCCNT = 1.
0

Generation of RDC excitation output and triggering of the ADC will be gated off.

Bit 14 – EXCOE Excitation Signal Output Enable bit

This bit will be used to control the behavior of the RDC excitation output signals only when the excitation signal generation is not active. If set, this bit will enable the outputs via I/O mux output enable and force the outputs of both signals to 0. If cleared, this bit will disable the outputs, resulting in a tri-stated condition. If the user enables the excitation signal output by setting EXCSYNCEN, RDC excitation outputs will take the values of the excitation signals generated by the module once the excitation signal synchronization period elapses, regardless of the EXCOE bit setting.
ValueDescription
1

RDC excitation output signals will be driven to 0 and enabled.
0

RDC excitation output signals will not be enabled, and pins are tri-stated.

Bits 3:0 – EXCFDIV[3:0]  Excitation Frequency Divider bit(2)

Divides the module input clock signal to generate the excitation clock signal and excitation output signals.

RDC excitation output = (RDC input clock / 8*(EXCFDIV+1))

ValueDescription
1111

RDC excitation output = RDC input clock / 128
1110

RDC excitation output = RDC input clock / 120
…
0001

RDC excitation output = RDC input clock / 16
0000

RDC excitation output = RDC input clock / 8