18.3.15 CIC Filter Input Timeout Counter Register
- The FILTOPR bit value may not
be modified when the ON (CICCON1[15]) bit is set. This bitfield should not
be written when FILTOEN(CICCON1[5]) =
1.
Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit
can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as
'0'; -n = Value at POR; '1' = bit is set;
'0' = bit is cleared; x = bit value is unknown
| Name: | CICTIMEOUT |
| Offset: | 0x001FC8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FILTOCNT[15:0] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FILTOCNT[15:0] | |||||||||
| Access | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | R/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FILTOPR[12:5] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FILTOPR[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 0 | 0 | ||||
Bits 31:16 – FILTOCNT[15:0] CIC Filter Input Timeout Counter bits
This counter is clocked from the system clock. If FILTOEN(CICCON1[5]) =
1 and FILTOPR(CICTIMEOUT[15:3]) is not 0x0000, the filter
input timeout counter will be reset and will begin counting when one of the CIC
filter input channels receives valid data from the ADC. The counter will stop
when valid data input on the other CIC channel is asserted.
Bits 15:8 – FILTOPR[12:5] CIC Filter Input Timeout Period bits(1)
Sets the time period in 8x multiples of the system clock before the filter interrupt timeout is triggered. The counter FILTOCNT will begin counting when the first data is received on any CIC input channel. If the counter value counts FILTOPR cycles before the data input is available on the other enabled channel, the FILTOERR(CICSTAT[19]) bit will be set and an error interrupt will be triggered.
| Value | Description |
|---|---|
0x1fff |
An error will be triggered if 65528 (0x1FFF * 8) clock cycles elapse between the valid data input on one of the CIC channels and the valid data input on the other CIC channel. |
| … | |
0x0002 |
An error will be triggered if 16 (0x0002 * 8) clock cycles elapse between the valid data input on one of the CIC channels and the valid data input on the other CIC channel. |
0x0001 |
An error will be triggered if 8 (0x0001 * 8) clock cycles elapse between the valid data input on one of the CIC channels and the valid data input on the other CIC channel. |
0x0000 |
Timeout is disabled. Setting FILTOPR to zero has the same effect as setting FILTOEN to 0. |
Bits 7:3 – FILTOPR[4:0] CIC Filter Input Timeout Period bits(1)
Sets the time period in 8x multiples of the system clock before the filter interrupt timeout is triggered. The counter FILTOCNT will begin counting when the first data is received on any CIC input channel. If the counter value counts FILTOPR cycles before the data input is available on the other enabled channel, the FILTOERR(CICSTAT[19]) bit will be set and an error interrupt will be triggered.
| Value | Description |
|---|---|
0x1fff |
An error will be triggered if 65528 (0x1FFF * 8) clock cycles elapse between the valid data input on one of the CIC channels and the valid data input on the other CIC channel. |
| … | |
0x0002 |
An error will be triggered if 16 (0x0002 * 8) clock cycles elapse between the valid data input on one of the CIC channels and the valid data input on the other CIC channel. |
0x0001 |
An error will be triggered if 8 (0x0001 * 8) clock cycles elapse between the valid data input on one of the CIC channels and the valid data input on the other CIC channel. |
0x0000 |
Timeout is disabled. Setting FILTOPR to zero has the same effect as setting FILTOEN to 0. |