18.3.13 CIC Status Register
- This bit is set by an invalid input event and cleared by the firmware.
- Writing to this bit has no effect.
Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit
can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as
'0'; -n = Value at POR; '1' = bit is set;
'0' = bit is cleared; x = bit value is unknown
| Name: | CICSTAT |
| Offset: | 0x001FC0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IISERR | FILTOERR | CICOUTOVF | BUSY | DONE | |||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/HC/HS | R/HC/HS | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DECIMCNT[11:8] | |||||||||
| Access | R/HC/HS | R/HC/HS | R/HC/HS | R/HC/HS | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DECIMCNT[7:0] | |||||||||
| Access | R/HC/HS | R/HC/HS | R/HC/HS | R/HC/HS | R/HC/HS | R/HC/HS | R/HC/HS | R/HC/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 20 – IISERR Invalid Input Sample Error bit(1)
| Value | Description |
|---|---|
1 |
An invalid input has been detected on an input channel. |
0 |
No invalid input event has occurred since this bit was last cleared. |
Bit 19 – FILTOERR CIC Filter Timeout Error bit
| Value | Description |
|---|---|
1 |
The value of the filter input counter FILTOCNT(CICTIMEOUT[31:16]) matches or exceeds the period value FILTOPR(CICTIMEOUT[15:3]). |
0 |
The filter input timeout condition has not occurred. |
Bit 18 – CICOUTOVF CIC Module Output Overflow bit
| Value | Description |
|---|---|
1 |
An output value has been written to the CICxDOUT registers before the previous value was read. |
0 |
No overflow condition has occurred. |
Bit 17 – BUSY CIC Module Input Busy bit(2)
| Value | Description |
|---|---|
1 |
Module is processing the input sample. |
0 |
Module idle, new input sample can be asserted. |
Bit 16 – DONE CIC Output Data Ready bit(2)
| Value | Description |
|---|---|
1 |
New output data is available. |
0 |
Module is idle or processing data. |
Bits 11:0 – DECIMCNT[11:0] DECIM Value from CICDECIM register
The DECIM(CICDECIM[11:0]) value is loaded into these bits when the first sample is processed. It will count down to 0 for each input sample processed.