18.3.1 RDC Control Register
Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit
can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as
'0'; -n = Value at POR; '1' = bit is set;
'0' = bit is cleared; x = bit value is unknown
| Name: | RDCCON |
| Offset: | 0x001F90 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CORDICSTART | |||||||||
| Access | R/S/HC | ||||||||
| Reset | 0 |
Bit 15 – ON RDC Enable bit
| Value | Description |
|---|---|
1 |
Module is enabled. |
0 |
Module is disabled. |
Bit 0 – CORDICSTART CORDIC Block Start bit
| Value | Description |
|---|---|
1 |
Begins a CORDIC calculation. The CXIN, CYIN and CANGIN bit fields should be loaded with valid inputs before setting this bit. Writes to the CXIN, CYIN or CANGIN bits will be ignored while CORDICSTART is set. This bit is cleared by hardware when the calculation is completed. |
0 |
The CORDIC block calculation is not in progress. |