18.3.5 RDC Excitation Signal Delay Register

Note:

This register is unused when ADCTRGDLY(RDCEXCCON[15]) = 0.
Writes to the register when ON(RDCCON[15]) = 1 will be ignored.

Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as '0'; -n = Value at POR; '1' = bit is set; '0' = bit is cleared; x = bit value is unknown

Name:	RDCEXCDLY
Offset:	0x001FA0


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	EXCFBDLY[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
							ADCTRGDLY[1:0]
Access							R/W	R/W
Reset							0	0

Bits 15:8 – EXCFBDLY[7:0] Excitation Signal Polarity Feedback Delay bits

A delay is inserted between excitation signal generation and the propagation of feedback to the RDC CIC filter. This value must be programmed to compensate for delays introduced by the resolver, external components, and ADC sampling time. The actual delay produced by the EXCFBDLY setting will be between the value of (EXCFBDLY + 1) and (EXCFBDLY + 2), due to the synchronization of the excitation clock with the system clock.

Value	Description
11111111	Delay of 256 system clock cycles
…
00000010	Delay of 3 system clock cycles
00000001	Delay of 2 system clock cycles
00000000	Delay of 1 system clock cycle

Bits 1:0 – ADCTRGDLY[1:0] ADC Trigger Delay bit

A phase delay is inserted between the RDC excitation clock output signal and the trigger signal to the ADC from the RDC. This value must be selected to ensure that the excitation signal does not transition to a new value during ADC sampling.

Value	Description
`11`	Delay of 3 RDC input clock cycles
`10`	Delay of 2 RDC input clock cycles
`01`	Delay of 1 RDC input clock cycle
`00`	Delay of 0 RDC input clock cycles