18.3.17 CIC Channel x Invalid Input Sample Status Register
Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit
can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as
'0'; -n = Value at POR; '1' = bit is set;
'0' = bit is cleared; x = bit value is unknown
| Name: | CICIISxSTAT |
| Offset: | 0x001FD0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| HIISCNT[11:8] | |||||||||
| Access | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| HIISCNT[7:0] | |||||||||
| Access | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LIISCNT[11:8] | |||||||||
| Access | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LIISCNT[7:0] | |||||||||
| Access | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | R/W/HC/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 27:16 – HIISCNT[11:0] Channel x High Invalid Input Sample Count bits
The number of input samples larger than the threshold defined by the THIGH(CICINTHR[31:16]) bits was detected during the calculation of the most recent CIC output value.
Bits 11:0 – LIISCNT[11:0] Channel x Low Invalid Input Sample Count bits
The number of input samples is smaller than the threshold defined by the TLOW(CICINTHR[15:0]) bits detected during the calculation of the most recent CIC output value.