18.3.11 CIC Control 1 Register
- Cleared by HW when BUSY is set.
- Writes to this bit will be
ignored when INSRC(CICCON1[31]) =
0or ON(CICCON1[15]) =0.
Legend: HC = bit is Cleared by Hardware; HS = bit is Set by Hardware; S = bit
can be Set only; R = Readable bit; W = Writable bit; U = Unimplemented bit, read as
'0'; -n = Value at POR; '1' = bit is set;
'0' = bit is cleared; x = bit value is unknown
| Name: | CICCON1 |
| Offset: | 0x001FB8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| INSRC | POLSEL | DEMODEN | CICUPDATE | ||||||
| Access | R/W | R/W | R/W | R/S/HC | |||||
| Reset | 0 | 0 | 1 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CH1EN | CH0EN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | ORDER | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FILTOEN | OUTSHIFT[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 31 – INSRC Filter Input Source Selection bits
| Value | Description |
|---|---|
1 |
Filter processes inputs from the module register CICxDIN. |
0 |
Filter processes inputs from an external source. |
Bit 30 – POLSEL Filter Polarity Source Selection bit
| Value | Description |
|---|---|
1 |
The filter uses the polarity bit (POLOVR(CICCON2[0])). |
0 |
The filter uses the RDC excitation signal for polarity. |
Bit 29 – DEMODEN Demodulation Enable bit
| Value | Description |
|---|---|
1 |
The filter will demodulate input values based on polarity controlled by POLSEL (CICCON1[30]) and POLOVR (CICCON2[0]). |
0 |
The filter will not demodulate input values. |
Bit 28 – CICUPDATE Filter Input Update Command bit(1,2)
Setting this bit triggers the processing of an input sample.
Bit 17 – CH1EN CIC Channel 1 Enable bit
| Value | Description |
|---|---|
1 |
Channel 1 is enabled. |
0 |
Channel 1 is disabled. Input signals are ignored. |
Bit 16 – CH0EN CIC Channel 0 Enable bit
| Value | Description |
|---|---|
1 |
Channel 0 is enabled. |
0 |
Channel 0 is disabled. Input signals are ignored. |
Bit 15 – ON CIC Enable bit
| Value | Description |
|---|---|
1 |
CIC filter enabled. The filter starts operating with the next input update event or when the CICUPDATE bit is set. |
0 |
CIC filter disabled. Input update events and the CICUPDATE bit toggles are ignored. |
Bit 13 – SIDL CIC Stop in Idle bit
| Value | Description |
|---|---|
1 |
The operation of the filter stopped when the device was in Idle mode. |
0 |
The operation of the filter continues when the device is in Idle mode. |
Bit 8 – ORDER CIC Filter Order bit
| Value | Description |
|---|---|
1 |
Filter order is 2 (two integrator stages, two difference stages). |
0 |
Filter order is 1 (one integrator stage, one difference stage). |
Bit 5 – FILTOEN CIC Filter Timeout Enable bit
| Value | Description |
|---|---|
1 |
The CIC filter input logic will trigger a timeout error if sufficient time elapses between inputs. |
0 |
The CIC filter input logic will not trigger a timeout error. |
Bits 4:0 – OUTSHIFT[4:0] Filter Output Shift bit
0 disables shifting. Shifting is done with
sign-extension.