27.2.6 FWDT Configuration Register
Legend: PO = Program Once bit
| Name: | FWDT |
| Offset: | 0xF20 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FWDTEN | SWDTPS[4:0] | WDTWIN[1:0] | |||||||
| Access | R/PO | R/PO | R/PO | R/PO | R/PO | R/PO | R/PO | R/PO | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WINDIS | RCLKSEL[1:0] | RWDTPS[4:0] | |||||||
| Access | R/PO | R/PO | R/PO | R/PO | R/PO | R/PO | R/PO | R/PO | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 15 – FWDTEN Watchdog Timer Enable bit
| Value | Description |
|---|---|
1 |
WDT is enabled in hardware. |
0 |
WDT controller via the ON bit (WDTCONL[15]). |
Bits 14:10 – SWDTPS[4:0] Sleep Mode Watchdog Timer Period Select bits
| Value | Description |
|---|---|
11111 |
Divide by 2 ^ 31 = 2,147,483,648 |
11110 |
Divide by 2 ^ 30 = 1,073,741,824 |
| ... | |
00001 |
Divide by 2 ^ 1, 2 |
00000 |
Divide by 2 ^ 0, 1 |
Bits 9:8 – WDTWIN[1:0] Watchdog Timer Window Select bits
| Value | Description |
|---|---|
11 |
WDT window is 25% of the WDT period. |
10 |
WDT window is 37.5% of the WDT period. |
01 |
WDT window is 50% of the WDT period. |
00 |
WDT Window is 75% of the WDT period. |
Bit 7 – WINDIS Watchdog Timer Window Enable bit
| Value | Description |
|---|---|
1 |
Watchdog Timer is in Non-Window mode. |
0 |
Watchdog Timer is in Window mode. |
Bits 6:5 – RCLKSEL[1:0] Watchdog Timer Clock Select bits
| Value | Description |
|---|---|
11 |
LPRC clock |
10 |
FRC clock |
01 |
Peripheral clock |
00 |
Reserved |
Bits 4:0 – RWDTPS[4:0] Run Mode Watchdog Timer Period Select bits
| Value | Description |
|---|---|
11111 |
Divide by 2 ^ 31 = 2,147,483,648 |
11110
|
Divide by 2 ^ 30 = 1,073,741,824 |
... |
|
00001 |
Divide by 2 ^ 1, 2 |
00000 |
Divide by 2 ^ 0, 1 |