Panel Swap Code Sequence

For a successful BTSEQ validation, a prior instruction (to BOOTSWP) is responsible for reading and loading the inactive panel BTSEQ number into a W-reg. The BOOTSWP instruction must operate on the same register to validate the value read.

The boot sequence number is a 12-bit unsigned value. The BTSEQ word format consists of two 12-bit values with BTSEQ [11:0] containing the true sequence number, and BTSEQ [23:12] containing its complement as shown in BOOTSWP Instruction. BTSEQ [127:24] is reserved and must read as all 0’s.

Panel Swap Code Example shows a panel swap example code.

; Example panel swap code sequence

    MOV      INACTIVE_BTSEQ, W1
    MOV      #label,W0
    BOOTSWP  W1
    GOTO     W0

label (code entry point)

Note 1: The GOTO instruction is assumed
to be located within both panels at the
same equivalent address. The “label”
address will be consistent but may be
in either panel depending upon whether
BOOTSWP succeeds or not.

Note 2: The BTSEQ value load may immediately
precede BOOTSWP but will incur
a RAW hazard stall.

If the BOOTSWP is enabled and the BTSEQ validation succeeds, BOOTSWP will be successful, and it will result in a panel swap and SR.Z = 1 and NVMCON.SOFTSWAP = 1.

If BOOTSWP is enabled but the BTSEQ validation fails, BOOTSWP will be unsuccessful. To indicate this result to subsequent code, BOOTSWP will drive SR.Z = 0. NVMCON.SOFTWAP will also not be set.

If BOOTSWP is not enabled but execution is attempted, no error will be flagged, and the instruction will execute as if a two-cycle NOP. Execution will then continue as normal (from the same panel).

The BOOTSWP instruction will always be fetched from the original active panel mapping. The instruction immediately following BOOTSWP may be any instruction other than another BOOTSWP and will be fetched from either the new or current active panel, depending upon the success or failure of the BOOTSWP operation.

Successful BOOTSWP: The CPU will attempt to fetch the instruction following BOOTSWP but will be stalled by the PBU. The PBU will then invalidate the cache and ISB. When complete, the original instruction fetch will be allowed to proceed but from the new active panel.

Unsuccessful BOOTSWP: The instruction following BOOTSWP will be fetched and executed as normal from the current active panel.

Should the user need to switch back and forth between panels at any point, code located at “label” (see Panel Swap Code Example) should test SR.Z or the NVMCON.SOFTSWAP status bit to determine whether or not the BOOTSWP was successful, then take the appropriate action. For applications where a “one way” swap is required, code at “label” in the current active panel can assume an unsuccessful panel swap and take appropriate action. Code at the same address within the new active panel can jump directly to the application code, knowing that the panel swap must have succeeded.

Figure 6-5 shows a BOOTSWP instruction flow diagram.

Figure 6-6 shows a panel swap sequence flow diagram