26.4.4 CCPx Status Register
- This is not a physical bit
location and will always read as ‘
0’. A write of ‘1’ will initiate the hardware event. - This bit has no effect when
CLKSEL[2:0] (CCPxCON1[10:8]) =
000or TMRSYNC =1.
| Name: | CCPxSTAT |
| Offset: | 0x1B0C, 0x1B3C, 0x1B6C, 0x1B9C, 0x1BCC, 0x1BFC, 0x1C2C, 0x1C5C, 0x1C8C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PRLWIP | TMRHWIP | TMRLWIP | RBWIP | RAWIP | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ICGARM | |||||||||
| Access | W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCPTRIG | TRSET | TRCLR | ASEVT | SCEVT | ICDIS | ICOV | ICBNE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 20 – PRLWIP CCPxPRL Write in Progress Status bit(2)
| Value | Description |
|---|---|
1 |
An update to the CCPxPRL register with the buffered contents is in progress. |
0 |
An update to the CCPxPRL register is not in progress. |
Bit 19 – TMRHWIP CCPxTMRH Write in Progress Status bit(2)
| Value | Description |
|---|---|
1 |
An update to the CCPxTMRH register with the buffered contents is in progress. |
0 |
An update to the CCPxTMRH register is not in progress. |
Bit 18 – TMRLWIP CCPxTMRL Write in Progress Status bit(2)
| Value | Description |
|---|---|
1 |
An update to the CCPxTMRL register with the buffered contents is in progress. |
0 |
An update to the CCPxTMRL register is not in progress. |
Bit 17 – RBWIP CCPxRB Write in Progress Status bit(2)
| Value | Description |
|---|---|
1 |
An update to the CCPxRB register with the buffered contents is in progress. |
0 |
An update to the CCPxRB register is not in progress. |
Bit 16 – RAWIP CCPxRA Write in Progress Status bit(2)
| Value | Description |
|---|---|
1 |
An update to the CCPxRA register with the buffered contents is in progress. |
0 |
An update to the CCPxRA register is not in progress. |
Bit 10 – ICGARM Input Capture Gate Arm bit(1)
A write of ‘1’ to this location will arm the input capture
gating logic for a one-shot gate event when ICGSM[1:0] = 01 or
10. Bit location reads as ‘0’ (see Table 26-8).
Bit 7 – CCPTRIG CCPx Trigger Status bit
| Value | Description |
|---|---|
1 |
Timer has been triggered and is running. |
0 |
Timer has not been triggered and is held in Reset. |
Bit 6 – TRSET CCPx Trigger Set Request bit(1)
A write of ‘1’ to this location will request a trigger of the
time base when TRIGEN = 1. The bit will clear automatically
after the trigger event has been generated, allowing a new trigger event to be
requested.
Bit 5 – TRCLR CCPx Trigger Clear Request bit(1)
A write of ‘1’ to this location will request a trigger
cancellation when TRIGEN = 1 and CCPTRIG = 1.
Bit clears automatically after the cancellation has completed, allowing a new
cancellation to be requested.
Bit 4 – ASEVT CCPx Auto-Shutdown Event Status/Control bit
| Value | Description |
|---|---|
1 |
A shutdown event is in progress; CCP outputs are in the Shutdown state. |
0 |
CCP outputs operate normally. |
Bit 3 – SCEVT Single Edge Compare Event Status bit
| Value | Description |
|---|---|
1 |
A single edge Compare event has occurred. |
0 |
A single edge Compare event has not occurred. |
Bit 2 – ICDIS Input Capture Disable bit
| Value | Description |
|---|---|
1 |
Event on Input Capture pin does not generate a capture event. |
0 |
Event on Input Capture pin will generate a capture event. |
Bit 1 – ICOV Input Capture Buffer Overflow Status bit
| Value | Description |
|---|---|
1 |
The Input Capture FIFO buffer has overflowed. |
0 |
The Input Capture FIFO buffer has not overflowed. |
Bit 0 – ICBNE Input Capture Buffer Status bit
| Value | Description |
|---|---|
1 |
Input Capture buffer has data available. |
0 |
Input Capture buffer is empty. |