26.4.2 CCPx Control Register 2
Note:
- This bit has no effect in
Timer modes, Output Compare modes or PWM modes. A write to the ICGARM
(CCPxSTAT[10]) bit will re-arm the one-shot gating circuit when ICGSM =
01or ICGSM =10. - This bit has no affect for Timer gating or Input Capture gating functions.
| Name: | CCPxCON2 |
| Offset: | 0x1B04, 0x1B34, 0x1B64, 0x1B94, 0x1BC4, 0x1BF4, 0x1C24, 0x1C54, 0x1C84 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OENSYNC | OCBEN | OCAEN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ICGSM[1:0] | AUXOUT[1:0] | ICS[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PWMRSEN | ASDGM | SSDG | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ASDG[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – OENSYNC Output Enable Synchronization bit
| Value | Description |
|---|---|
1 |
Update by the output enable bits occurs on the next time base Reset or rollover. |
0 |
Update by output enable bits occurs immediately. |
Bit 25 – OCBEN Output Enable/Steering Control bit
| Value | Description |
|---|---|
1 |
The OCx pin is controlled by the CCP module and produces an Output Compare or PWM signal. |
0 |
The OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral multiplexed on the pin. |
Bit 24 – OCAEN Output Enable/Steering Control bit
| Value | Description |
|---|---|
1 |
The OCx pin is controlled by the CCP module and produces an Output Compare or PWM signal |
0 |
The OCx pin is not controlled by the CCP module; the pin is available to the port logic or another peripheral multiplexed on the pin. |
Bits 23:22 – ICGSM[1:0] Input Capture Gating Source Mode Control bits(1)
| Value | Description |
|---|---|
11 |
Reserved |
10 |
One-Shot mode; falling edge from gating source will disable future capture
events (CDIS = 1). |
01 |
One-Shot mode; rising edge from gating source will enable future capture
events (CDIS = 0). |
00 |
Level Sensitive mode; a high level from gating source will enable future capture events; a low level will disable future capture events. |
Bits 20:19 – AUXOUT[1:0] Auxiliary Output Signal Selection bits
| Value | Description |
|---|---|
11 |
The signal output depends on the Module Operating mode (see Table 26-10). |
10 |
Signal output depends on Module Operating mode (see Table 26-10). |
01 |
Signal output depends on Module Operating mode (see Table 26-10). |
00 |
No signal output on aux_out |
Bits 18:16 – ICS[2:0] Input Capture Source Select bits
Bit 15 – PWMRSEN CCPx Output Compare Restart Enable bit
| Value | Description |
|---|---|
1 |
ASEVT (CCPxSTAT[4]) bit clears automatically at the beginning of the next output compare period, after the shutdown input has ended. |
0 |
ASEVT (CCPxSTAT[4]) bit must be cleared in software to resume the output compare activity on output pins. |
Bit 14 – ASDGM CCPx Auto-Shutdown/Gate Control bit(2)
| Value | Description |
|---|---|
1 |
Wait until next time base Reset or rollover for an Output Compare pin shutdown to occur. |
0 |
The Output Compare pin shutdown event occurs immediately. |
Bit 12 – SSDG CCPx Software Shutdown/Gate Control bit
| Value | Description |
|---|---|
1 |
Manually force an auto-shutdown, the Timer Clock Gate or Input Capture signal gate event (setting of ASDGM bit still applies). |
0 |
Normal module operation |
Bits 7:0 – ASDG[7:0] CCPx Auto-Shutdown/Gating Source Enable bits
| Value | Description |
|---|---|
1 |
ASDG source n is enabled. |
0 |
ASDG source n is disabled. |